Gate Capping Layer Formation After Residue-Safe Etch Back
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Solution Overview
Problem
The semiconductor industry faces challenges in effectively removing residues over gate structures during etch back operations, which can lead to over-etching issues, material loss, and poor reliability of semiconductor devices due to non-uniform thicknesses and poorly formed overlying structures.
Innovation Solution
A combination of specific cleaning chemicals with pH values between 5.0 and 8.0, including hydrogen peroxide and ozone, is used to remove boron-containing polymer residues, followed by a fluoride drive-in operation to form a capping layer with controlled thickness and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etch back operations are performed to remove residues, then residue removal is achieved, but over-etching occurs causing material loss and non-uniform thickness
Solution Approach 1:
The patent changes the chemical parameters of the cleaning solution by controlling pH between 5.0 and 8.0, and uses specific combinations of chemicals (hydrogen peroxide, ozone, water) to achieve effective residue removal without over-etching. This parameter optimization resolves the contradiction by finding the optimal chemical environment that removes residues while preserving gate structure integrity
Solution Approach 2:
The patent introduces a carefully controlled cleaning solution as an intermediary substance that mediates between the residue (contaminant) and the gate structure (sensitive component). The cleaning solution with specific pH and chemical composition acts as a controlled intermediary that removes residues without directly attacking the gate structure, thus preventing material loss while achieving reliable cleaning
2Productivity
If aggressive cleaning methods are used to remove residues, then residue removal efficiency is improved, but gate structure integrity deteriorates due to over-etching
Solution Approach 1:
The patent achieves both high residue removal efficiency and gate structure uniformity by changing the chemical parameters of the cleaning solution. Specifically, controlling pH between 5.0 and 8.0 and using controlled concentrations of hydrogen peroxide and ozone creates a cleaning environment that is aggressive enough to remove residues but gentle enough to preserve gate structure integrity and uniformity
Solution Approach 2:
The patent applies a controlled cleaning process that uses chemical substances (hydrogen peroxide, ozone) at optimized levels to achieve complete residue removal without excessive action that would damage the gate structure. The cleaning is sufficient to remove all residues but controlled to prevent over-etching, thus maintaining manufacturing precision
3Quantity of substance
If cleaning chemicals with extreme pH values are used, then residue removal capability is enhanced, but material loss increases
Solution Approach 1:
The patent changes the pH parameter from extreme values to a moderate range (5.0-8.0), and adjusts the chemical composition to include hydrogen peroxide, ozone, and water in controlled proportions. This parameter optimization maintains strong residue removal capability while significantly reducing gate material loss compared to extreme pH cleaning methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes residues while minimizing material loss, improving device performance and reliability by ensuring uniformity and stability of the capping layer, thereby enhancing the overall semiconductor structure.
Implementation Method 1
A combination of specific cleaning chemicals with pH values between 5.0 and 8.0, including hydrogen peroxide and ozone, is used to remove boron-containing polymer residues
Implementation Method 2
followed by a fluoride drive-in operation to form a capping layer with controlled thickness and uniformity
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.