Gate Cavity Dielectric Layout for Low-Capacitance RF Switches
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Solution Overview
Problem
Current RF switches fabricated on SOI substrates face challenges in balancing on-resistance (Ron) and off-state capacitance (Coff), where reducing one parameter tends to increase the other, leading to higher power consumption and unwanted noise.
Innovation Solution
A semiconductor device with a cavity, such as an air gap, is formed over the gate body without an etch stop layer, using a dielectric layer to define the cavity's bottom, which reduces off-state capacitance by controlling the effective dielectric constant of the interconnect layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor manufacturing processes are used to lower on-resistance, then on-resistance is reduced, but off-state capacitance increases
Solution Approach 1:
The cavity is segmented into multiple regions: a first cavity portion extending through the interconnect layer to expose the gate body, and a second cavity portion extending partially through the dielectric layer while leaving a portion of the dielectric layer over the gate body. This segmentation allows different regions to serve different functions in controlling both on-resistance and off-state capacitance.
Solution Approach 2:
The dielectric layer is selectively retained only over the gate body region while removing etch stop layers in other areas. This local quality modification creates a specific dielectric constant distribution that reduces off-state capacitance without compromising on-resistance performance.
2Object-generated harmful factors
If conventional semiconductor manufacturing processes are used to minimize off-state capacitance, then off-state capacitance is reduced, but on-resistance increases
Solution Approach 1:
The effective dielectric constant of the interconnect layer is changed by removing the etch stop layer and selectively retaining only a portion of the dielectric layer over the gate body. This parameter change reduces off-state capacitance while the cavity structure maintains low on-resistance through proper gate exposure.
3Object-generated harmful factors
If a cavity is formed through the interconnect layer, then off-state capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The etch stop layer is removed in advance before forming the cavity, creating a prepared surface that facilitates subsequent cavity formation. This preliminary action simplifies the overall manufacturing process by pre-conditioning the structure for easier cavity creation.
Solution Approach 2:
The dielectric layer acts as an intermediary that is selectively retained over the gate body to define the cavity bottom. This intermediary layer provides a controlled interface that simplifies cavity formation while maintaining the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes off-state capacitance and on-resistance, reducing power consumption and noise in RF switches by optimizing the dielectric constant of the interconnect layer.
Implementation Method 1
a portion of the dielectric layer is over the gate body and defines a bottom of the cavity
Data Source
AI summary
A semiconductor device includes a transistor including source/drain regions and a gate, the gate having a gate body. An etch stop layer is over the source/drain regions but not over the gate body. An interconnect layer is over the transistor and includes a dielectric layer. A cavity extends partially through the interconnect layer above the gate, and a portion of the dielectric layer is over the gate body and defines a bottom of the cavity. The cavity provides a mechanism to reduce both on-resistance and off-capacitance for applications such as radio frequency switches.