Gate CD Control via Dummy Gate Pitch and Width
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Solution Overview
Problem
As IC fabrication advances, controlling the critical dimension (CD) of gate electrodes becomes increasingly challenging due to the limitations of lithographic projection tools, particularly at the 45 nm node, where conventional methods fail to provide sufficient process margin for accurate gate CD control.
Innovation Solution
Incorporating neighboring dummy feature pitch and width restrictions in the design of the local environment around these features on both sides, allowing for sub-resolution assist features on the mask, which helps maintain a consistent gate pitch and improves CD control by widening the process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic projection tools are used for gate patterning, then manufacturing process simplicity is maintained, but gate CD control precision deteriorates due to resolution limits at 45 nm node
Solution Approach 1:
The patent introduces neighboring dummy features as intermediary elements that mediate between the lithographic projection tool and the active gate feature. These dummy features, positioned adjacent to the active gate on both sides, serve as buffer structures that control the local environment during lithography and etching processes, thereby improving gate CD control without requiring changes to the fundamental lithographic tooling
Solution Approach 2:
The patent applies local quality by creating asymmetric dummy feature configurations tailored to specific layout conditions. The dummy features on opposite sides of the active gate can have different pitches and dimensions, optimized for the local pattern density and etch environment on each side, thereby providing targeted CD control where it is most needed
2Manufacturing precision
If dummy features are added to improve gate CD control, then manufacturing precision improves, but device complexity increases due to additional mask design constraints
Solution Approach 1:
The patent segments the dummy feature design into independent controllable parameters on each side of the active gate. The pitch, width, and spacing of dummy features can be independently optimized for each side based on local requirements, allowing flexible adaptation to different layout scenarios without requiring complete redesign of the entire gate array
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the pitch and dimensions of neighboring dummy features to optimize etch environment. By adjusting these geometric parameters, the local pattern density and etch selectivity are modified to achieve better CD control, with the ability to tune parameters based on specific process conditions
3Manufacturing precision
If pitch restrictions are applied to neighboring dummy features on both sides, then gate CD uniformity improves, but design flexibility deteriorates
Solution Approach 1:
The patent introduces dynamic adaptability by allowing the dummy feature pitch and dimensions to vary based on local layout conditions. Rather than imposing rigid uniform pitch restrictions across all gates, the design permits adjustment of dummy feature parameters according to the specific pattern density, gate spacing, and etch environment of each local region, thereby maintaining CD uniformity while preserving design flexibility
Data Source
AI summary
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.