Replacement Gate Formation With On-Fin CD Feedback Control
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Solution Overview
Problem
Current semiconductor manufacturing processes lack a cost-effective and efficient method for controlling gate critical dimensions (CDs) and profiles, leading to variations that affect transistor performance and yield rates due to unknown process factors and lack of immediate feedback in lithography steps.
Innovation Solution
A gate formation control system that measures gate CDs at 'on-fin' regions to fine-tune etching recipes, allowing for precise control of gate trench formation and replacement gate stack deposition, thereby achieving uniformity across wafers and chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional inspection equipment is used to measure gate CDs and profiles, then measurement capability is provided, but immediate feedback to lithography steps is not achieved and production throughput is reduced
Solution Approach 1:
The patent implements a feedback mechanism where gate CD measurements are taken after etching, and the measured values are used to adjust subsequent etch processing parameters. This closed-loop control enables real-time process correction without halting production, resolving the contradiction between measurement precision and productivity
Solution Approach 2:
The patent establishes correlation data between gate CDs and etching recipes in advance through preliminary experiments. This pre-computed relationship allows immediate determination of adjusted etch parameters from measured gate CDs without requiring complex real-time calculations, maintaining high production throughput while achieving precise control
2Ease of operation
If process control settings are made universal, then ease of operation is improved, but process variations from unknown factors cannot be addressed
Solution Approach 1:
The patent transitions from static universal process control settings to dynamic adaptive control. The system dynamically adjusts etch parameters based on actual measured gate CD values from each wafer or batch, enabling the process to adapt to variations caused by unknown factors while maintaining ease of operation through automated adjustment
Solution Approach 2:
The patent changes the etching recipe parameters based on measured gate CD deviations. By correlating gate CD measurements with specific etch parameter adjustments (such as power, pressure, or gas flow), the system achieves precise manufacturing control while keeping the operator interface simple and automated
3Manufacturing precision
If gate formation control is improved, then manufacturing precision is enhanced, but system complexity increases
Solution Approach 1:
The patent discards the complexity of developing and implementing complex real-time control algorithms by instead recovering and utilizing pre-established correlation data between gate CDs and etching recipes. This approach achieves high manufacturing precision through simple lookup and adjustment based on measured values, avoiding the need for complex control systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides accurate gate CD and profile characterization, improving transistor performance and yield rates by correlating 'on-fin' gate CD measurements with etching recipes, enabling real-time adjustments to maintain targeted gate dimensions and reduce within-wafer and wafer-to-wafer non-uniformity.
Implementation Method 1
perform an etching process on the target wafer to form a gate trench
Implementation Method 2
forming a metal gate stack in the gate trench
Data Source
AI summary
A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.