Gate Driving Circuit Layout for Balanced Clock Line Loads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices experience image quality degradation due to capacitance and load deviations between gate signal lines, leading to screen abnormalities when the gate driving circuit is integrated within the display panel.
Innovation Solution
The gate driving circuit is integrated into the display panel in a gate in panel (GIP) type, with specific line structures and an overcoat layer design that prevents overlap between cathode electrodes and clock signal lines, ensuring stable signal and power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate driving circuit is integrated into the display panel (GIP type), then device complexity is reduced and productivity is improved, but capacitance deviation and load deviation occur between signal lines, causing image quality degradation
Solution Approach 1:
The patent applies local quality by creating different structural configurations for different groups of signal lines. Specifically, first clock signal lines are positioned to overlap with metal layers while second clock signal lines are positioned to not overlap with metal layers. This local differentiation allows each signal line group to have optimized capacitance characteristics, compensating for the overall capacitance deviation problem while maintaining the benefits of GIP integration.
Solution Approach 2:
The patent employs asymmetry by intentionally creating asymmetric positioning of clock signal lines relative to metal layers. The first and second clock signal lines are asymmetrically arranged with respect to the metal layers, resulting in different capacitance values that can be used to balance and compensate for load deviations across the gate driving circuit, thereby improving image quality while maintaining integration.
2Ease of operation
If clock signal lines are positioned closer to the display area, then ease of operation is improved, but capacitance deviation occurs due to overlap with metal layers, causing load deviation
Solution Approach 1:
The patent applies local quality by creating different structural configurations for different groups of signal lines. Specifically, first clock signal lines are positioned to overlap with metal layers while second clock signal lines are positioned to not overlap with metal layers. This local differentiation allows each signal line group to have optimized capacitance characteristics, compensating for the overall capacitance deviation problem while maintaining the benefits of GIP integration.
Solution Approach 2:
The patent employs parameter changes by varying the physical positioning parameters of clock signal lines relative to metal layers. By changing the spatial arrangement parameter (overlap vs. no overlap), the capacitance parameter is directly modified. This allows precise control over capacitance values to achieve uniform load distribution across the gate driving circuit.
Data Source
AI summary
A display panel and a display device which may remove load deviation between clock signal lines. More specifically, the display device includes a substrate including a display area capable of displaying an image and a non-display area disposed around the display area, the display area including a subpixel and a gate line for driving the subpixel; a gate driving panel circuit disposed in the non-display area and configured to output a gate signal to the gate line; a plurality of clock signal lines disposed in the non-display area and positioned to be farther from the display area than the gate driving panel circuit to supply a plurality of clock signals to the gate driving panel circuit; an overcoat layer disposed on the plurality of clock signal lines and the gate driving panel circuit; and a light emitting element included in the subpixel, comprising a cathode electrode disposed on the overcoat layer and extending from the display area to the non-display area, wherein the cathode electrode is disposed not to overlap the plurality of clock signal lines.