Gate Driving Circuit Clocking to Mitigate TFT PBTS
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Solution Overview
Problem
Thin film transistors in gate driving circuits are susceptible to positive bias temperature stress (PBTS) due to continuous turn-on states during emission periods, leading to potential threshold voltage shifts and reliability issues.
Innovation Solution
A gate driving circuit design incorporating a Q-node controller, QB-node controller, pull-up and pull-down transistors, and inverter transistors controlled by clock signals to manage transistor voltages, reducing PBTS and enhancing hydrogen capture effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin film transistor is maintained in a continuous turn-on state during emission period, then the emission function is ensured, but positive bias temperature stress (PBTS) occurs leading to threshold voltage shifts and reliability degradation
Solution Approach 1:
The patent applies periodic action by controlling the transistor to switch between on and off states in a periodic manner during the emission period, rather than maintaining a continuous on state. This periodic switching reduces the accumulation of positive bias temperature stress while still ensuring adequate emission function, thereby improving transistor reliability without completely disabling the emission capability.
2Reliability
If the transistor is turned off repeatedly to reduce PBTS, then reliability improves, but the emission continuity may be affected
Solution Approach 1:
The patent implements periodic action with carefully controlled duty cycles, where the transistor switches between on and off states. The off periods are sufficiently short to allow stress relief but long enough to prevent excessive threshold voltage shifts, while the on periods maintain emission continuity. This periodic switching strategy balances reliability improvement with emission duration requirements.
3Reliability
If oxide transistors are increased in number and density to enhance hydrogen capture effect, then threshold voltage variation is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple oxide transistors into integrated circuit structures where they work together to enhance the hydrogen capture effect. By combining these transistors in specific configurations, the patent achieves improved threshold voltage stability through increased hydrogen capture while managing the overall device complexity through integrated design rather than separate discrete components.
Solution Approach 2:
The patent changes physical parameters such as the number and density of oxide transistors to enhance the hydrogen capture effect. By adjusting these parameters, the patent reduces threshold voltage variation and improves reliability, while the parameter changes are implemented in a controlled manner to manage device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively mitigates PBTS, improves transistor reliability, and reduces threshold voltage variations, thereby enhancing the performance and longevity of the gate driving circuit.
Implementation Method 1
enhancing a hydrogen (H) capture effect through an increase in the number of oxide transistors constituting the gate driving circuit and an increase in density of titanium (Ti)
Data Source
AI summary
A gate driving circuit and a display apparatus including the same are disclosed. The gate driving circuit includes a Q-node controller configured to control a voltage of a Q-node by first and second clock signals and a start signal or an output signal of an upstream stage, a QB-node controller configured to control a voltage of a QB-node by the second clock signal, a pull-up transistor configured to pull-up drive a logic output terminal in response to the voltage of the Q-node, a pull-down transistor configured to pull-down drive the logic output terminal in response to the voltage of the QB-node, a first inverter transistor configured to supply a gate-low voltage to an output terminal in response to the first clock signal, and a second inverter transistor configured to supply a gate-high voltage to the output terminal in response to a voltage of the logic output terminal.