Gate Driving Circuit Layout for Low-Stress Multi-Line Scan Output
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Solution Overview
Problem
The size of the gate driving circuit in display devices is increased by the number of transistors in each stage circuit, leading to potential leakage currents, image quality degradation, and reduced lifespan due to voltage stress and frequent driving.
Innovation Solution
A gate driving circuit with reduced transistors in stage circuits and adjusted voltage levels to minimize stress, using dummy stage circuits and a specific connection structure for carry signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of transistors in each stage circuit is increased, then the gate driving circuit can generate gate signals for more gate lines, but the size of the gate driving circuit increases
Solution Approach 1:
The gate driving circuit is divided into multiple stage circuits that operate sequentially. Each stage circuit generates gate signals for a subset of gate lines, and the stages are connected through carry signal lines that coordinate the operation between stages. This segmentation allows the circuit to handle more gate lines without proportionally increasing the size of each individual stage circuit.
2Adaptability or versatility
If the number of transistors in each stage circuit is increased, then more gate signals can be generated, but leakage current increases and image quality degrades
Solution Approach 1:
The first stage circuit includes dummy stage circuits that perform preliminary operations before the main stage circuits operate. These dummy circuits prepare the carry signal lines and establish proper voltage levels in advance, ensuring that when the main stage circuits activate, they do so with proper initialization that prevents leakage current and ensures signal integrity for reliable display operation.
3Productivity
If transistors are driven more times, then more gate signals can be generated, but transistor degradation increases and lifespan shortens
Solution Approach 1:
The stage circuits operate in periodic sequences where each stage activates in turn based on clock signals. The carry signal lines coordinate this periodic operation, allowing efficient gate signal generation while distributing the operational burden across multiple stages rather than continuously stressing a single transistor configuration, thereby extending overall circuit lifespan.
Data Source
AI summary
The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.