Gate Driving Circuit Topology for Stable Output in Compact Displays
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Solution Overview
Problem
Existing display devices face challenges in achieving a compact size while maintaining stable output of gate signals, which is crucial for efficient operation of pixels.
Innovation Solution
A driving circuit design incorporating specific transistor configurations and a capacitor to stabilize node voltages, allowing for alternating clock signals to efficiently output gate signals of varying levels, thereby reducing voltage fluctuations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional gate driving circuit is used, then gate signals can be output, but the circuit size becomes large and voltage stability deteriorates
Solution Approach 1:
The patent combines multiple transistors (first through fifth transistors) and capacitors into an integrated stage structure that shares common nodes and signal paths. This merging of components reduces the overall circuit area while maintaining voltage stability through the coordinated operation of the transistor network and capacitor connections.
Solution Approach 2:
The patent utilizes voltage level changes at intermediate nodes (first node, second node, third node) to control the switching states of multiple transistors. By changing voltage parameters at these nodes based on clock signals and start signals, the circuit achieves stable gate signal output with reduced area.
2Power
If a conventional gate driving circuit is used, then gate signals can be output, but power consumption increases
Solution Approach 1:
The patent employs periodic clock signals (first clock signal and second clock signal with half-period shift) to control the switching of transistors in sequence. This periodic action enables the circuit to regenerate gate signals at regular intervals, maintaining stable output while reducing power consumption by keeping transistors in low-power states between cycles.
Solution Approach 2:
The patent incorporates feedback paths where the output of one transistor stage feeds back to control earlier stages. The voltage at the third node, for example, feeds back to control the first transistor, creating a feedback mechanism that maintains stable gate signal output while optimizing power consumption through efficient transistor switching.
3Adaptability or versatility
If voltage fluctuations occur in the circuit, then signal levels can vary, but gate signal stability deteriorates
Solution Approach 1:
The patent places capacitors at strategic nodes (second node and third node) that act as voltage buffers before the signal reaches the output stage. These capacitors cushion voltage fluctuations by storing and releasing charge, preventing large voltage variations from propagating through the circuit and maintaining stable gate signal levels.
Solution Approach 2:
The patent introduces intermediate nodes (first node, second node, third node) with capacitors that act as mediators between the input signals and the final gate signal output. These intermediate stages filter and stabilize voltage variations, allowing the circuit to adapt to different input conditions while maintaining stable output.
Data Source
AI summary
A driving circuit includes a first transistor connected between a first terminal to which a start signal is input and a first node and comprising a gate connected to a second node; a second transistor connected between a first clock terminal to which a first clock signal is input and the second node and comprising a gate connected to a second terminal to which a first voltage is supplied; a third transistor connected between the first node and the second node; and a fourth transistor connected between the first node and a gate of the third transistor and comprising a gate connected to the second node.