Gate Clad Pattern Reduces Parasitic Capacitance in OLED TFTs
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Solution Overview
Problem
In organic light emitting diode (OLED) displays, parasitic capacitance between the source and drain electrodes and the gate electrode causes signal delay, which affects the performance and efficiency of the thin film transistors.
Innovation Solution
The design includes a gate electrode with a metal gate pattern and a metal oxide gate clad pattern, an oxide semiconductor layer, and source and drain electrodes in contact with the oxide semiconductor layer, along with a specific insulating layer structure and etch stopping pattern to reduce or eliminate parasitic capacitance, using indium tin oxide (ITO) for the metal oxide layers and forming patterns with halftone masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the source electrode and drain electrode are overlapped with the gate electrode to form thin film transistor, then the device can function as a transistor, but parasitic capacitance is formed in the gate insulating layer causing signal delay
Solution Approach 1:
The gate insulating layer is removed from the region where the source and drain electrodes overlap with the gate electrode. This extraction of the insulating layer eliminates the parasitic capacitance formation while maintaining the transistor's basic structure and function.
Solution Approach 2:
Instead of having the gate insulating layer cover the entire gate electrode including the overlap region, the patent inverts the conventional structure by exposing the gate electrode in the overlap region. This allows direct contact between the gate electrode and the semiconductor layer without the insulating barrier, eliminating parasitic capacitance.
2Loss of time
If the gate insulating layer is removed to reduce parasitic capacitance, then signal delay is reduced, but the gate electrode may be exposed and require additional protection
Solution Approach 1:
The gate electrode serves multiple functions: it provides the gate control function and simultaneously acts as a protective layer for the semiconductor layer in the overlap region. By removing the gate insulating layer, the gate electrode directly protects the semiconductor layer while enabling low parasitic capacitance operation.
Solution Approach 2:
The protective function previously provided by the gate insulating layer is merged with the gate electrode itself. The gate electrode now serves both as the control electrode and as the protective layer, eliminating the need for a separate gate insulating layer in the overlap region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces or eliminates signal delay caused by parasitic capacitance, enhancing the performance and efficiency of the thin film transistors in OLED displays by increasing the distance between the gate and source/drain electrodes and using indium tin oxide to improve hole injection and light emitting efficiency.
Implementation Method 1
using indium tin oxide (ITO) for the metal oxide layers and forming patterns with halftone masks... improves hole injection and light emitting efficiency
Implementation Method 2
An organic light emitting layer may be positioned on the pixel electrode... the organic light emitting diode may include a pixel electrode
Data Source
AI summary
A thin film transistor includesa gate electrode including a gate pattern positioned on a substrate and a gate clad pattern covering the gate pattern. An oxide semiconductor layer is positioned on the gate electrode. A source electrode and a drain electrode are positioned on the oxide semiconductor layer. The source electrode and the drain electrode are ach in contact with end portions of the oxide semiconductor layer.