Gate Clock Signal Compensator for Jitter Mitigation
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Solution Overview
Problem
Display panels, particularly liquid crystal display panels, suffer from horizontal line defects due to time differences or 'jitter' in the gate clock signal, which deteriorate display quality.
Innovation Solution
A display apparatus and method that includes a gate clock signal compensator, which generates an inner clock signal based on a vertical start signal and periodic data, compares it with the gate clock signal to determine time differences, and selects either the gate clock signal or the inner clock signal to compensate for jitter, increasing the level of the selected signal to produce a compensated gate clock signal for the gate driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate clock signal is used directly without compensation, then the device complexity is low, but the display quality deteriorates due to horizontal line defects caused by jitter
Solution Approach 1:
The patent introduces a gate clock signal compensator as an intermediary component between the timing controller and the gate driver. This compensator generates an inner clock signal based on the vertical start signal and compares it with the gate clock signal to detect jitter, then selects and outputs a compensated clock signal to eliminate horizontal line defects while maintaining acceptable device complexity
Solution Approach 2:
The gate clock signal compensator implements a feedback mechanism by continuously comparing the gate clock signal with the inner clock signal, detecting time differences (jitter), and adjusting the output clock signal accordingly. This feedback loop ensures that display quality is maintained by compensating for jitter in real-time
2Reliability
If the gate clock signal has jitter, then the device complexity remains low, but the reliability of display output deteriorates due to horizontal line defects
Solution Approach 1:
The gate clock signal compensator serves as a mediator that improves the reliability of display output by filtering out jitter from the gate clock signal before it reaches the gate driver, thereby preventing horizontal line defects without significantly increasing device complexity
Solution Approach 2:
The system prepares an inner clock signal in advance based on the vertical start signal, which serves as a reference for compensating jitter in the gate clock signal. This beforehand preparation ensures that reliable timing information is available to prevent display defects
Data Source
AI summary
A display apparatus includes a display panel displaying an image and including a gate line and a data line, a gate driver outputting a gate signal to the gate line, a data driver outputting a data signal to the data line, a timing controller outputting a vertical start signal and a gate clock, and a gate clock signal compensator generating an inner clock signal based on the vertical start signal, selecting one of the gate clock signal and the inner clock signal based on a comparison result of a time difference between the gate clock signal and the inner clock signal and a reference time which corresponds to tolerance of jitter of the gate clock signal, increasing a level of the selected clock signal, and outputting the increased clock signal to the gate driver, where the gate driver generates the gate signal based on the increased clock signal.