Gate Clock Generator Adjusting Signal Widths for Low-Temperature Display Stability

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Solution Overview

Problem

Conventional display devices face issues with gate driver connection failures and increased manufacturing costs due to separate IC chip configurations, and amorphous silicon gate drivers experience reduced electron mobility at lower temperatures, leading to abnormal voltage levels and incorrect image display.

Innovation Solution

A display device with a gate clock generator that adjusts voltage levels of control signals to the gate driver, incorporating a signal converter and controller to manage gate clock signals and output enable signals, ensuring correct image display even at low temperatures by modifying the logic high period of gate clock signals and inverting logic levels as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the gate driver is provided in a separate IC chip configuration, then the manufacturing process is simpler, but connection failure occurs and manufacturing cost increases

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidconnection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate driver is integrated directly into the display panel substrate, merging two previously separate components (display panel and gate driver IC chip) into a single unified structure. This eliminates the connection interface between the IC chip and gate lines, thereby preventing connection failures while maintaining manufacturing simplicity through simultaneous fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If the gate driver is simultaneously manufactured with the display panel, then manufacturing cost is reduced and connection reliability is improved, but electron mobility changes with temperature causing abnormal voltage levels

Engineering Contradiction:
Improveconnection reliabilityVSAvoidvoltage level precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a temperature compensation mechanism that dynamically adjusts the gate turn-on signal voltage levels based on ambient temperature conditions. By monitoring temperature changes and modifying the voltage parameters accordingly, the system compensates for the temperature-dependent electron mobility variations in amorphous silicon, maintaining precise voltage levels across different temperature ranges while preserving the integrated manufacturing benefits.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If amorphous silicon is used for gate driver circuit elements, then simultaneous manufacturing with display panel is enabled, but response speed is rapidly reduced at low temperatures

Engineering Contradiction:
Improvesimultaneous manufacturing capabilityVSAvoidresponse speed
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent implements temperature-dependent voltage adjustment for the gate turn-on signals. At lower temperatures, the system increases the voltage level of gate turn-on signals to compensate for reduced electron mobility in amorphous silicon circuit elements. This parameter change maintains the response speed and driving capability of the gate driver across varying temperature conditions while preserving the benefit of simultaneous manufacturing with the display panel.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2017818B1Display device and method for driving the same
Publication Date: 2017.04.05 SAMSUNG DISPLAY CO LTD
  • EP2017818B1 patent drawing
  • EP2017818B1 patent drawing
  • EP2017818B1 patent drawing

AI summary

A display device includes a display panel, a gate clock generator and a gate driver. The display panel includes a plurality of gate lines connected to a plurality of pixels. The gate clock generator generates a plurality of gate clock signals in which a width of a logic high period of a first gate clock signal is smaller than that of other gate clock signals during one frame period. The gate driver sequentially applies gate turn-on signals to the plurality of gate lines according to the gate clock signal and a gate clock bar signal having a phase opposite to the other gate clock signals.