Gate Clock Generator for Variable Pulse Width Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate clock generators in display devices are limited by fixed gate pulse phases and widths, which restrict the flexibility in timing control and pulse modulation, leading to inefficiencies in driving display panels, particularly in organic light-emitting display devices.
Innovation Solution
A gate clock generator comprising a counter, buffer control signal generator, and output unit that adjusts gate ON voltage timing and pulse width based on control data, allowing for variable pulse width, duty ratio, slew rate, and gate pulse modulation, enabling independent control of gate clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional level shifter is used to generate gate clocks, then the gate clock can be output according to preset timing control signals, but the gate pulse phase and width are fixed and cannot be varied
Solution Approach 1:
The gate clock generator is divided into separate functional modules: a counter unit that generates counting values, a buffer control signal generator that creates control signals based on counting values, and an output unit that generates gate clocks based on control signals. This segmentation allows independent optimization of each module to achieve variable pulse width and phase while maintaining overall system manageability.
Solution Approach 2:
The patent implements dynamic control by allowing the counter to count up to different threshold values (first threshold and second threshold) that can be programmed via control data. This enables the pulse width and phase of gate clocks to be dynamically adjusted without changing the hardware structure, resolving the contradiction between adaptability and complexity.
2Adaptability or versatility
If sequential shifting is used for gate clocks, then the gate driver can operate in a structured manner, but the gate pulses applied to display panel lines have the same phase and pulse width
Solution Approach 1:
The patent applies local quality by generating different buffer control signals for different gate clock outputs. The buffer control signal generator creates first buffer control signals and second buffer control signals with different characteristics based on different counting thresholds, allowing each gate line to receive customized pulse widths and phases while maintaining structured operation.
3Object-affected harmful factors
If fixed timing control signals are used, then the system operation is simplified, but electromagnetic interference and brightness deviations occur
Solution Approach 1:
The patent changes the timing parameters of gate clocks by allowing the counter to reach different threshold values (first threshold for rising edge, second threshold for falling edge) based on programmable control data. This parameter adjustment optimizes the timing characteristics to reduce electromagnetic interference and brightness deviations while maintaining manageable system complexity through software-controlled parameter setting.
Data Source
AI summary
The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.