Gate Driving Clock Scheme for Stable High-Temperature Display Panels
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Solution Overview
Problem
Gate controlling signals are abnormal due to characteristics of semiconductor devices, leading to charge loss and potential changes at key nodes, affecting display effect in high-temperature environments.
Innovation Solution
A gate driving unit with a clock signal design that includes transitions between active and inactive levels in writing frames and holding frames to stabilize potential at key nodes, reducing power consumption and maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are placed in a DC state to reduce power consumption, then power consumption is reduced, but leakage currents increase in high-temperature environments causing charge loss and abnormal gate controlling signals
Solution Approach 1:
The patent applies periodic action by switching the clock signal between DC state (for power saving) and AC state (for signal stability) based on frame type. In holding frames, the clock signal maintains DC state to reduce power consumption. In writing frames, the clock signal transitions to AC state with multiple transitions between active and inactive levels to prevent charge loss and maintain signal integrity at key nodes, thus resolving the contradiction between power consumption and signal reliability.
2Use of energy by moving object
If the clock signal remains in inactive state during holding frames, then power consumption is reduced, but potential stability at key nodes deteriorates due to leakage currents
Solution Approach 1:
The patent implements periodic action by designing the clock signal to have different characteristics in holding frames versus writing frames. During holding frames, the clock signal stays in DC state with minimal transitions to maintain low power consumption. During writing frames, the clock signal introduces multiple transitions between active and inactive levels to refresh and stabilize potentials at key nodes, counteracting leakage current effects while maintaining overall power efficiency.
Solution Approach 2:
The patent applies preliminary action by ensuring that before potential instability caused by leakage currents becomes problematic, the clock signal introduces transitions to refresh the charges at key nodes. This proactive approach prevents potential drift and maintains signal integrity without requiring continuous AC operation, thus balancing power consumption with potential stability.
3Reliability
If transitions between active and inactive levels are increased to maintain signal integrity, then gate controlling signals remain effective, but power consumption increases
Solution Approach 1:
The patent resolves this contradiction by applying periodic action with frame-based clock signal design. In writing frames where signal integrity is critical, the clock signal includes multiple transitions between active and inactive levels to maintain effective gate controlling signals. In holding frames where display content remains static, the clock signal adopts DC state with minimal transitions to reduce power consumption. This time-varying approach ensures signal reliability when needed while minimizing power consumption during stable display periods.
Data Source
AI summary
A gate driving unit and a display panel are provided by the present disclosure. In a writing frame of the display panel, a clock signal has a plurality of transitions between an active level state and an in active level state. In a plurality of holding frames of the display panel, the clock signal has a plurality of first periods holding the inactive level state, and the clock signal has a plurality of transitions between the active level state and the inactive level state in a second period between two adjacent first periods.