Gate Driving Circuit Timing for Stable High-Temperature Scan Pulses
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Solution Overview
Problem
N-type oxide semiconductor transistors in shift registers experience increased leakage current at high temperatures, leading to unstable output due to negative shift in threshold voltage, causing voltage drops at set nodes and preventing normal operation of scan pulses.
Innovation Solution
A gate driving circuit design that includes a first clock generator for output clock pulses and a second clock generator for output control clock pulses, with specific phase relationships and overlapping waveforms to prevent current leakage from set nodes, ensuring stable operation by managing the timing and voltage of clock pulses and control pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional oxide semiconductor transistor is used in a shift register, then the transistor can be turned off in the output period, but at high temperatures the threshold voltage shifts negatively causing leakage current that prevents normal operation
Solution Approach 1:
The patent changes the timing parameters of clock pulses applied to switching devices. Specifically, it uses different phase relationships between clock pulses for different switching devices, ensuring that when one device is turning off, another device is turning on to maintain proper voltage levels at set nodes, thereby compensating for temperature-induced threshold voltage shifts
Solution Approach 2:
The patent dynamically adjusts the timing relationships between clock pulses based on the operational state of the shift register. By using multiple phases of clock pulses with specific phase differences, the system adapts the switching timing to prevent leakage current at high temperatures while maintaining proper operation at lower temperatures
2Object-generated harmful factors
If the threshold voltage of the oxide semiconductor transistor shifts negatively at high temperature, then the transistor cannot be turned off properly generating leakage current, but this leakage current causes voltage at the set node to fall rapidly or fail to rise
Solution Approach 1:
The patent applies clock pulses to switching devices in a predetermined sequence with specific timing relationships. Before a switching device that needs to turn off completely, another device is activated to pre-establish the voltage level at the set node, preventing voltage collapse from leakage current
Solution Approach 2:
The patent introduces intermediate switching devices and timing control mechanisms between the clock signal and the oxide semiconductor transistors. These intermediate control elements coordinate the switching actions to ensure that voltage at set nodes is maintained stable even when transistors exhibit leakage current at high temperatures
3Device complexity
If clock pulses are applied to switching devices with simple timing, then the circuit is easy to control, but this simple timing allows overlapping high sections that cause charge leakage from set nodes
Solution Approach 1:
The patent segments the clock pulse signal into multiple phases with different timing characteristics. Different switching devices receive different phase-shifted clock pulses, creating non-overlapping or partially overlapping high sections that prevent charge leakage while maintaining controllable complexity
Solution Approach 2:
The patent uses asymmetric timing relationships between clock pulses for different switching devices. The phase differences are specifically designed so that the high sections of clock pulses follow a pattern where adjacent pulses overlap by a predetermined time, creating a asymmetric timing structure that prevents leakage current
Data Source
AI summary
Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse.