Gate Clock Signal Modulation for Display Panel Charging Rate
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Solution Overview
Problem
Conventional gate drivers in display devices often result in insufficiently lowered gate signals, leading to reduced charging rates and display panel performance, as the potential of the gate signal can be influenced by the overlapping time of scanning start and gate clock signals, affecting both the current and subsequent stages.
Innovation Solution
A display device incorporating a gate clock signal modulating unit and generator to modulate the width of the gate clock signal pulses overlapping with the scanning start signal, ensuring a sufficient potential of the gate signal is maintained, thereby preventing a decrease in charging rate and improving gate driver performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate clock signal and scanning start signal are overlapped to generate gate signals, then the gate driver can be simplified and integrated into the display panel, but the potential of the gate signal may be insufficiently lowered, causing reduced charging rate and display performance
Solution Approach 1:
The patent applies preliminary action by extending the pulse width of the gate clock signal before it overlaps with the scanning start signal. This ensures that the gate signal potential is sufficiently lowered in advance, preventing charging rate reduction and performance degradation in subsequent stages of the gate driver.
2Reliability
If the pulse width of gate clock signal is extended to ensure sufficient potential lowering, then gate signal reliability is improved, but the device complexity and control difficulty increase
Solution Approach 1:
The patent applies local quality by selectively extending the pulse width of the gate clock signal only during the period when it overlaps with the scanning start signal, rather than uniformly extending it throughout. This localized adjustment ensures sufficient potential lowering where needed while maintaining simplicity in other portions of the signal cycle.
3Ease of manufacture
If conventional gate driver integration is used, then manufacturing simplicity is improved, but charging rate uniformity across display panel stages deteriorates
Solution Approach 1:
By extending the gate clock signal pulse width in advance before the overlap period with the scanning start signal, the patent ensures that each stage of the gate driver maintains consistent charging rates. This preliminary adjustment compensates for potential signal degradation, achieving uniform charging performance across all display panel stages while keeping the integrated gate driver structure.
Data Source
AI summary
A display device includes a display panel, a gate driver, a gate clock signal modulating unit, and a gate clock signal generator. The display panel includes gate lines and pixels connected to the gate lines via respective switching elements. The gate driver includes stages configured to output gate signals to the gate lines. The gate clock signal modulating unit is configured to modulate an input gate clock signal based on a scanning start signal to generate an output gate clock signal. The gate clock signal generator is configured to generate a clock signal based on the gate clock signal and output the clock signal to the gate driver. The gate clock signal modulating unit is configured to modulate a width of a pulse of the input gate clock signal overlapping a pulse of the scanning start signal.