Display Gate Clock Voltage Holding for Faster Response
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Solution Overview
Problem
Existing display devices face challenges in maintaining the gate clock signal at a predetermined voltage during the blank period due to current leakage, leading to potential display quality issues and delays in the gate clock signal.
Innovation Solution
Incorporating a voltage maintainer in the clock generator to maintain the gate clock signal at a fixed reference voltage during the blank period, and using impedance control circuits to manage the slew rate and timing of the gate clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate clock signal is allowed to float during the blank period, then the circuit complexity is reduced, but the voltage stability deteriorates due to current leakage
Solution Approach 1:
The gate clock signal is connected to its own power supply terminal through a pull-up resistor, enabling it to self-maintain its voltage level during the blank period without requiring external intervention or additional active circuitry
Solution Approach 2:
A pull-up resistor is introduced as an intermediary component between the gate clock signal and the power supply terminal, providing a passive mechanism to maintain voltage stability during the blank period
2Reliability
If the gate clock signal is maintained at fixed voltage during blank period, then the display quality is improved, but the device complexity increases
Solution Approach 1:
The gate clock signal automatically maintains its own voltage level during the blank period through the pull-up resistor connection to the power supply terminal, achieving reliable display quality without requiring complex external control circuits
3Speed
If the slew rate of gate clock signal is increased, then the response speed is improved, but the signal integrity may deteriorate
Solution Approach 1:
The impedance of the gate clock signal line is optimized to control the slew rate, achieving fast response speed while maintaining signal integrity through proper impedance matching
Data Source
AI summary
A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.