Multi-Layer Hard Mask for Gate Conductor Line Edge Roughness
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Solution Overview
Problem
Conventional lithographic processes face limitations in achieving small feature sizes due to resolution issues and uncontrolled line edge roughness (LER) during the formation of gate conductor structures, which are exacerbated by resist erosion and corner rounding defects.
Innovation Solution
A method involving a multi-layer hard mask scheme is employed, where a tri-layer hard mask is formed over a gate electrode layer, with specific etching processes using photoresist patterns to etch each layer sequentially, reducing resist budget and improving line edge roughness by maintaining the integrity of the gate conductor profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick photoresist and single hard mask are used to etch fine gate conductor lines, then the resist budget is sufficient for etching, but severe corner rounding defects occur at the upper portion of the hard mask resulting in worsened line edge roughness
Solution Approach 1:
The patent divides the single hard mask into multiple layers (first hard mask layer, second hard mask layer, and third hard mask layer). This segmentation allows each layer to serve specific functions: the first layer provides the primary etch mask, the second layer protects against corner rounding, and the third layer serves as an anti-reflective coating. This multi-layer structure eliminates corner rounding defects while maintaining manufacturing precision.
Solution Approach 2:
The patent transitions from a single-layer hard mask to a multi-layer hard mask structure, adding vertical dimensionality to the mask system. This dimensional change enables better control over the etching process by providing different functional layers at different heights, thereby preventing corner rounding and improving line edge roughness.
2Manufacturing precision
If conventional lithography is used to fabricate small features, then the process is simple and cost-effective, but resolution and accuracy are insufficient to consistently fabricate minimum size features
Solution Approach 1:
The patent segments the lithography process into multiple steps involving a multi-layer hard mask system. Instead of relying on a single lithography exposure, the process uses sequential patterning with the first, second, and third hard mask layers, each contributing to the final feature accuracy. This segmentation enables conventional lithography to achieve precision comparable to advanced lithography methods.
Solution Approach 2:
The patent performs preliminary actions by forming the first hard mask layer with specific thickness and material properties before the actual patterning step. The second and third layers are also prepared in advance to provide protection and anti-reflective properties, ensuring that the final patterning achieves the required resolution and accuracy.
3Reliability
If a single hard mask is used for etching, then the process is simple and fast, but resist erosion and pattern collapse occur during the etching process
Solution Approach 1:
The patent segments the mask function across three distinct layers, where the first hard mask layer provides the primary pattern definition, the second hard mask layer protects against erosion during etching, and the third hard mask layer provides additional structural support. This segmentation prevents pattern collapse and maintains pattern integrity throughout the etching process.
Solution Approach 2:
The patent applies beforehand cushioning by placing the second and third hard mask layers over the first hard mask layer before the etching process begins. These additional layers act as a protective cushion that prevents resist erosion and pattern collapse during etching, ensuring pattern integrity is maintained.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of fine semiconductor structures with improved line edge roughness and reduced resist budget, enhancing the accuracy and precision of gate conductor fabrication by protecting the first hard mask from corner rounding erosion.
Implementation Method 1
A photoresist pattern is then formed on the multi-layer hard mask
Implementation Method 2
A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist
Data Source
AI summary
A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.