Gate Conductor Spacer Formation for Semiconductor Device Manufacturing
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in filling high-K dielectric and metal gate conductors into small gaps due to the scaling down of semiconductor devices, which complicates the formation of a stable gate stack configuration.
Innovation Solution
A 'replacement spacer' process is introduced, where a gate conductor is formed as a spacer on the sidewall of a reserved material layer, allowing for the formation of a gate stack in a relatively larger space, making it easier to perform compared to conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the replacement gate process is used to fill high-K dielectric and metal gate conductor in a small gap, then a gate stack configuration with high-K gate dielectric and metal gate conductor can be achieved, but the manufacturing difficulty increases significantly due to the scaling down of semiconductor devices
Solution Approach 1:
The patent applies preliminary action by forming shielding layers and shielding spacers before forming the gate conductor. The shielding layer is deposited on the substrate, source and drain regions are formed with the shielding layer as a mask, then a shielding spacer is formed on the sidewall of the shielding layer. This preliminary structure preparation creates a controlled environment that facilitates subsequent gate conductor formation without the difficulties of direct filling in small gaps.
Solution Approach 2:
The shielding layer and shielding spacer serve as intermediary structures that mediate between the substrate/source-drain regions and the gate conductor. These intermediary elements provide a temporary framework that enables precise positioning and formation of the gate conductor, which would be difficult to achieve through direct filling methods in scaled-down devices.
2Productivity
If the gap size is reduced due to device scaling, then device density increases, but the difficulty of filling materials into the gap increases
Solution Approach 1:
The patent transitions from a planar filling approach to a three-dimensional spacer-based approach. Instead of attempting to fill the gap horizontally between source and drain regions, the gate conductor is formed vertically on the sidewall of the shielding layer through spacer deposition. This dimensional change from 2D gap filling to 3D spacer formation on sidewalls enables precise material placement even in scaled-down devices.
Solution Approach 2:
The shielding layer and shielding spacer are formed in advance to create a predefined structure that guides the gate conductor formation. This preliminary action establishes the exact position and dimensions of the gate conductor region before material deposition, eliminating the uncertainties associated with filling small gaps directly.
Data Source
AI summary
Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.