Gate Conductor Structure with Variable Thickness for Reduced Resistance

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Solution Overview

Problem

In semiconductor manufacturing, the self-aligned dielectric cap in contact structures is prone to erosion, leading to shorts and dielectric breakdown, and a thick cap increases gate resistance due to reduced conductive material volume.

Innovation Solution

A semiconductor device design featuring gate structures with a self-aligned dielectric cap having a middle portion with less vertical thickness than the end portions, and a method involving forming gate conductor structures with a middle portion thicker than the end portions, and a second conductor with a greater width than the first conductor to prevent cap erosion and maintain a thick cap, thereby reducing gate resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the self-aligned dielectric cap is made thick to prevent erosion and shorts, then reliability is improved, but gate resistance increases due to reduced conductive material volume

Engineering Contradiction:

Improveprevention of source/drain contact to conductive material shortsVSAvoidgate resistance

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The gate conductor structure is designed with non-uniform thickness, having a middle portion with greater vertical thickness than end portions. This local variation in thickness allows the conductive material volume to be increased specifically in the region where it is most needed for current conduction, thereby reducing gate resistance without compromising the overall dielectric cap thickness required for reliability

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The solution transitions from considering only the horizontal dimensions to incorporating vertical dimension variation in the gate conductor structure. By making the middle portion taller in the vertical direction, the patent creates additional conductive material volume that reduces resistance without affecting the lateral dimensions or the dielectric cap thickness

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If the self-aligned dielectric cap is made thick to prevent erosion, then manufacturing precision is improved, but device complexity increases due to deep conductive material recess

Engineering Contradiction:

Improveprocess margin for self-aligned contact formationVSAvoidconductive material recess depth

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Instead of making the dielectric cap uniformly thick throughout, the patent inverts the approach by making the gate conductor structure itself have variable thickness. The middle portion of the gate conductor is made taller while the dielectric cap thickness can be reduced in corresponding regions, thereby achieving the required precision without the need for deep recesses in the conductive material

Inventive Principle:

Principle #13The other way round (Inversion)

3Ease of manufacture

If the gate conductor structure is made with uniform thickness, then ease of manufacture is improved, but gate resistance increases due to reduced conductive material volume

Engineering Contradiction:

Improvegate conductor structure fabricationVSAvoidgate resistance

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The gate conductor structure transitions from a static uniform thickness design to a dynamic variable thickness design where the middle portion is elevated. This structural evolution optimizes the conductive path without requiring complex multi-step fabrication processes

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11264278B1Transistor with reduced gate resistance and improved process margin of forming self-aligned contact

Publication Date: 2022.03.01 NAN YA TECH

AI summary

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a second conductor and a plurality of air gaps. The two gate structures are located on a surface of a semiconductor material substrate. The first conductor is disposed between the two gates structures. The barrier is disposed between the first conductor and the gate structure. The second conductor is disposed on the first conductor. The air gaps are disposed at two sides of the second conductor. A width of the second conductor is greater than a width of the first conductor.