Gate Connection Layout in STI CMOS to Suppress Hump Phenomenon
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Solution Overview
Problem
The existing semiconductor devices experience a hump phenomenon in static characteristics due to divots in the trench isolation structure, leading to instability in breakdown voltage and transistor performance, particularly in CMOS transistors with low-breakdown voltage.
Innovation Solution
The semiconductor device design features a p-type drain region surrounding the p-type source region, with a gate connection portion that crosses the boundary between the trench insulation structure and the active region, preventing immediate channel formation under the gate connection portion and thus suppressing the hump phenomenon while maintaining area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench insulation structure is formed in the semiconductor device, then isolation between active regions is achieved, but divots in the trench structure cause hump phenomenon leading to instability in breakdown voltage and transistor performance
Solution Approach 1:
The gate connection portion is extracted and positioned to cross the boundary between the trench insulation structure and the active region, specifically avoiding the divot region. This extraction of the gate connection from the problematic divot area eliminates the hump phenomenon while maintaining electrical connectivity.
Solution Approach 2:
The gate connection portion is designed with specific local positioning characteristics, crossing the boundary at a location that avoids the divot region. This local quality adjustment ensures that the gate connection interacts with the trench insulation structure in a way that prevents channel formation under the connection portion, thereby suppressing the hump phenomenon.
2Reliability
If the gate connection portion crosses the boundary between trench insulation structure and active region, then channel formation under the gate connection portion is prevented, but device complexity increases
Solution Approach 1:
The gate connection portion serves multiple functions: it provides electrical connectivity to the gate electrode, crosses the trench insulation boundary to reach the active region, and simultaneously acts as a structure that prevents unwanted channel formation. This multi-functionality reduces the need for additional separate structures.
Solution Approach 2:
The gate connection portion is merged with the gate electrode structure, forming an integrated component that performs both connection and channel suppression functions. This merging eliminates the need for separate channel suppression structures, thereby reducing overall device complexity.
Data Source
AI summary
A semiconductor device includes: a chip having a main surface; a trench insulation structure that defines an active region in the main surface; a first conductivity type well region formed in the active region; a second conductivity type first impurity region formed in the well region; a second impurity region formed in the well region and surrounding the first impurity region in a plan view; a gate electrode formed on the well region between the first impurity region and the second impurity region, and surrounding the first impurity region in a plan view; a gate insulating film formed between the gate electrode and the well region; a gate contact portion formed on the trench insulation structure; and a gate connection portion that crosses the second impurity region from a boundary between the trench insulation structure and the active region and connects the gate contact portion and the gate electrode.