Gate Electrode Connection Structure for Scaled MOSFET Stability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability and structural stability to maintain performance.
Innovation Solution
Incorporating a connection structure with a rounded inner and outer side surface on the gate electrodes, which are physically connected to enhance structural stability and prevent collapse, and using EUV lithography for precise patterning to ensure uniformity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties and reliability deteriorate
Solution Approach 1:
The connection structure is designed with rounded inner and outer side surfaces instead of sharp corners. This curvature reduces stress concentration at corners, preventing structural collapse of the gate electrode while maintaining the scaled-down device dimensions. The rounded geometry provides mechanical reinforcement without increasing the overall device area.
2Stability of the object's composition
If the connection structure has rounded surfaces to prevent gate electrode collapse, then structural stability is improved, but manufacturing complexity increases
Solution Approach 1:
The curvature radius of the rounded surfaces is specifically controlled within the range of 0.05 to 0.15 times the pitch between adjacent gate electrodes. This parameter optimization ensures adequate structural stability while maintaining compatibility with existing EUV lithography manufacturing capabilities, avoiding excessive manufacturing complexity.
3Strength
If the first outer side surface length is optimized relative to gate electrode pitch, then mechanical support is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first outer side surface length is designed to be 0.87 to 1.0 times the pitch between gate electrodes, providing sufficient mechanical support through moderate over-design rather than minimal sufficient design. This approach ensures adequate structural reinforcement while keeping manufacturing precision requirements within achievable limits for EUV lithography.
Data Source
AI summary
Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a cell disposing region and a first block border region, a plurality of gate electrodes on the cell disposing region and extending to the first block border region in a first direction to be parallel to each other, the gate electrodes including a first and second gate electrode, which are adjacent to each other, and a first connection structure on the first block border region, wherein the first connection structure is configured to physically connect the first and second gate electrodes to each other.