Ferroelectric Gate Connection Layout for Low-Voltage MOSFET Switching
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing power density due to high subthreshold swing limitations in silicon-based MOSFETs, making it difficult to achieve low supply voltages necessary for further miniaturization and integration.
Innovation Solution
Incorporating a ferroelectric material layer in the semiconductor device to form a negative capacitance ferroelectric capacitor, which increases overall capacitance and amplifies voltage applied to the gate electrode, thereby improving switching speed and reducing subthreshold swing below 60 mV/decade.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon-based MOSFET is used, then the device structure is simple and manufacturing is easy, but the subthreshold swing is limited to above 60 mV/decade and power density increases exponentially
Solution Approach 1:
The patent employs a composite material structure consisting of a ferroelectric material layer (such as hafnium oxide, barium strontium titanium oxide, or lead zirconate titanate) integrated with the gate electrode and gate insulating layer. This composite structure creates a negative capacitance effect that enables subthreshold swing below 60 mV/decade while maintaining compatibility with existing CMOS manufacturing processes, thus resolving the contradiction between ease of manufacture and subthreshold swing performance
Solution Approach 2:
The patent changes the electrical parameters of the gate structure by introducing a ferroelectric material layer with specific dielectric constant and thickness parameters. By controlling the thickness of the ferroelectric layer (typically 5-50 nm) and selecting materials with appropriate ferroelectric properties, the gate capacitance is modified to produce negative capacitance, enabling subthreshold swing improvement without fundamentally changing the manufacturing process
2Productivity
If the transistor size is miniaturized to increase integration density, then the degree of integration increases, but the drive voltage decreases and power density increases exponentially
Solution Approach 1:
The patent changes the voltage amplification parameter of the gate structure by introducing negative capacitance through the ferroelectric material layer. This enables the transistor to achieve higher effective gate voltage with lower supply voltage, allowing miniaturized transistors to maintain adequate drive strength while reducing power density and enabling further integration density improvement
3Power
If the supply voltage is reduced to lower power density, then power consumption decreases, but it becomes difficult to achieve very low supply voltage due to thermal emission-based physical operating characteristics
Solution Approach 1:
The patent utilizes the ferroelectric phase transition properties of the ferroelectric material layer, which exhibits spontaneous polarization that can be switched between positive and negative states. This phase transition capability enables voltage amplification where a small change in gate voltage produces a larger change in channel potential, allowing operation at supply voltages below the conventional 60 mV/decade limit and achieving power density reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a ferroelectric capacitor with negative capacitance enhances voltage amplification and improves transistor switching speed, enabling subthreshold swing reduction, thus addressing the limitations of silicon-based MOSFETs and supporting further miniaturization and integration.
Implementation Method 1
the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group
Implementation Method 2
The first conductive connection group includes a ferroelectric material layer
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.