Gate Connection Pattern Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
There is a need for a method to easily form division patterns and connection patterns in logic devices with gate structures, as existing methods are inefficient.
Innovation Solution
A semiconductor device is designed with gate structures on an insulation structure, source/drain layers, semiconductor patterns extending through the gate structures, division patterns, and a connection pattern that contacts the upper portions of the gate structures and division patterns, optimizing the electrical connection and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a connection pattern is formed to connect gate structures, then electrical connection between gate structures is improved, but parasitic capacitance increases
Solution Approach 1:
The connection pattern is designed to extend in the first direction (horizontal) rather than vertically connecting, changing the dimensional approach to electrical connection. This horizontal extension allows connection between gate structures while minimizing vertical overlap that would increase parasitic capacitance.
Solution Approach 2:
The connection pattern is positioned to contact only the lower portions of the gate structures, creating a localized connection approach. This selective contact at specific locations (lower portions rather than upper portions) reduces the overall overlap area and thus minimizes parasitic capacitance while maintaining electrical connectivity.
2Productivity
If division patterns are formed to divide gate structures, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The division patterns are merged with the insulation structure, forming an integrated insulating and dividing component. This merging eliminates the need for separate division structures, reducing manufacturing steps and complexity while achieving effective gate structure division for higher device integration.
3Reliability
If connection pattern contacts upper portions of gate structures, then electrical connection is improved, but parasitic capacitance increases
Solution Approach 1:
Instead of contacting the upper portions of the gate structures as conventionally done, the connection pattern is inverted to contact the lower portions. This inverted approach maintains electrical connection functionality while reducing the overlap area between the connection pattern and gate structures, thereby minimizing parasitic capacitance.
Data Source
AI summary
A semiconductor device includes gate structures on an insulation structure, the gate structures disposed in a second direction substantially parallel to an upper surface of the insulation structure, source/drain layers at opposite sides, respectively, of each gate structure in a first direction intersecting the second direction, semiconductor patterns disposed in a third direction substantially perpendicular to the upper surface of the insulation structure, the semiconductor patterns extending through each of the gate structures and contacting the source/drain layers, a first division pattern between the gate structures, and a connection pattern extending into and contacting an upper portion of the first division pattern and upper portions of the gate structures adjacent to the first division pattern, a lower surface of the connection pattern being lower than upper surfaces of the gate structures and an upper surface of the connection pattern being higher than the upper surfaces of the gate structures.