Gate Contact Formation Above Active Region for Packing Density

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Solution Overview

Problem

In integrated circuits, the conventional method of forming gate contacts above isolation regions rather than active regions leads to inefficient use of space, resulting in an area penalty due to the need for minimum spacing to avoid electrical shorts.

Innovation Solution

The method involves forming a gate contact cavity above the active region by removing portions of the gate cap layer and sidewall spacer, followed by the creation of a conductive gate plug and additional spacers, allowing for the formation of conductive structures directly above the active region while maintaining electrical integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate contacts are formed above isolation regions to avoid electrical shorts, then electrical reliability is improved, but chip area increases due to minimum spacing requirements

Engineering Contradiction:

Improveelectrical reliabilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The gate contact is repositioned from a lateral arrangement (above isolation region) to a vertical arrangement (directly above active region through gate cap and spacer), utilizing the vertical dimension to resolve the spacing conflict and reduce chip area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of avoiding the active region by placing contacts above isolation regions, the invention inverts the approach by deliberately positioning the gate contact above the active region and using spacer structures to prevent electrical shorts

Inventive Principle:

Principle #13The other way round (Inversion)

2Productivity

If gate contacts are positioned above active regions, then packing density increases, but risk of electrical shorts increases

Engineering Contradiction:

Improvepacking densityVSAvoidelectrical short risk

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

A spacer structure is introduced as an intermediary element between the gate contact and the active region, providing physical separation and preventing direct electrical contact while allowing the contact to be positioned above the active region

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate contact structure is segmented into multiple components (contact region, gate cap, spacer) with distinct functions, allowing the contact to be positioned above the active region while the spacer provides electrical isolation

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9947589B1Methods of forming a gate contact for a transistor above an active region and the resulting device

Publication Date: 2018.04.17 GLOBALFOUNDRIES US INC

AI summary

A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.