Self-Aligned Gate Contact Over Active Regions
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Solution Overview
Problem
The fabrication of 3D semiconductor devices faces challenges in advanced lithography, process integration, wet and dry etching, and gate formation, particularly due to short-channel effects and the need for improved device structures and processes that address current leakage issues in transistors with gate lengths below 20 nm.
Innovation Solution
A semiconductor device fabrication process that forms gates on a substrate by removing portions of a gate layer, partially filling openings with dielectric materials, and forming a self-aligned contact gate structure with a metal cap layer and liner, allowing for accurate placement of gates over active regions without breaking vacuum, thus preventing damage and improving device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate replacement is used to form permanent gates, then gate structure can be formed, but processing complexity increases and device yield decreases
Solution Approach 1:
The patent forms permanent metal gates directly during the initial gate formation process using a metal layer deposited before trench isolation, eliminating the need for subsequent dummy gate replacement. This preliminary action of forming the actual gate structure early in the process avoids additional processing steps and complexity.
Solution Approach 2:
The patent removes the conventional dummy gate formation and replacement steps from the process flow. By directly forming permanent metal gates in the initial stages, it extracts and eliminates the unnecessary dummy gate creation, patterning, and replacement operations that complicate the manufacturing process.
2Manufacturing precision
If gates are formed before contact structures, then self-aligned contacts can be achieved, but processing integration becomes more challenging
Solution Approach 1:
The patent forms permanent metal gates and fills trenches with dielectric material before forming contact structures. This preliminary formation of gates and isolation structures establishes precise alignment references that guide subsequent contact hole formation, achieving self-aligned contacts without requiring complex alignment procedures.
Solution Approach 2:
The patent uses the gate structure and trench dielectric as intermediary elements that facilitate precise contact alignment. The gates serve as physical references that mediate the alignment between contact structures and active regions, simplifying the overall process integration despite the sequential formation approach.
3Productivity
If advanced lithography is used for patterning nano-scaled transistors, then transistor density increases, but fabrication challenges increase
Solution Approach 1:
The patent performs preliminary patterning of the gate layer and trench regions before forming the metal gates and contact structures. This early patterning using advanced lithography establishes the high-density transistor layout, and subsequent steps follow the established patterns without requiring additional lithography, thereby achieving high density while managing fabrication complexity.
4Length of moving object
If gate length is reduced below 20 nm, then device scaling improves, but short-channel effects increase causing current leakage
Solution Approach 1:
The patent forms permanent metal gates with precise dimensions before trench isolation and contact formation. This preliminary gate formation ensures accurate gate length control at scaled dimensions, and the subsequent trench filling and contact formation process maintains the integrity of these scaled gates, preventing short-channel effects and current leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process eliminates the need for dummy gate replacement, reduces processing complexity, and enhances device performance by forming permanent gates before contact structures, enabling precise self-aligned contacts and improved electrical isolation, thereby addressing current leakage issues and increasing device yield.
Implementation Method 1
forming a first structure on the substrate in a processing system without breaking vacuum
Implementation Method 2
forming a first structure on the substrate in a processing system without breaking vacuum
Implementation Method 3
forming a planarized surface that comprises a surface of the gates and a surface of the third dielectric material
Data Source
AI summary
A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.