Gate Contact Capping Structure to Prevent Semiconductor Leakage
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to increased complexity and power dissipation, with leakage currents occurring due to the thinning of dielectric caps during gate contact formation, which reduces the yield of semiconductor devices.
Innovation Solution
A selective deposition process is employed to form a capping material over the thinned dielectric cap in the gate contact opening, increasing the distance between source/drain and gate contacts and preventing leakage currents, thereby improving the yield of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the dielectric cap is thinned during gate contact formation, then the manufacturing process can be simplified, but leakage currents occur between source/drain and gate contacts
Solution Approach 1:
A capping material is deposited over the dielectric cap in the gate contact opening before the gate contact is formed. This preliminary capping action protects the thinned dielectric cap from direct exposure to the gate contact, preventing leakage currents while maintaining the simplified manufacturing process.
Solution Approach 2:
The capping material serves as an intermediary layer between the thinned dielectric cap and the gate contact. This intermediate layer prevents direct electrical contact between the gate and source/drain regions, eliminating the leakage path that would otherwise occur due to the thinned dielectric cap.
2Productivity
If geometry size is scaled down, then production efficiency increases and costs decrease, but power dissipation increases
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of the device through the capping structure. The capping material changes the electrical field distribution and reduces leakage current, thereby reducing power dissipation while maintaining the scaled-down geometry for high production efficiency.
3Reliability
If the capping material is deposited selectively, then leakage currents are prevented, but the process complexity increases
Solution Approach 1:
The capping material is deposited selectively only in the gate contact opening region, not over the entire wafer. This localized deposition approach prevents leakage currents at the critical gate contact area while minimizing the added process complexity compared to a full-wafer deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The selective deposition of capping material effectively prevents leakage currents, enhancing the yield and reliability of semiconductor devices by maintaining the integrity of the dielectric cap during the formation of gate contacts.
Implementation Method 1
selectively depositing a capping material on the protective structure
Data Source
AI summary
The method for forming a semiconductor device includes forming a gate structure over a substrate; forming a plurality of source/drain structures in the substrate and on opposite sides of the gate structure; forming a source/drain contact on one of the plurality of source/drain structures; etching back the source/drain contact; forming a protective structure over the etched back source/drain contact; forming a dielectric layer over the gate structure and the protective structure; etching the dielectric layer to form an opening that exposes the gate structure and the protective structure; selectively depositing a capping material on the protective structure; after selectively depositing the capping material, forming a gate contact in the opening.