Gate Contact Structure for Copper Filling and Low-Resistance Wiring
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Solution Overview
Problem
Semiconductor devices face challenges in copper filling margin and resistance during the copper damascene method, particularly in securing adhesion, resistance due to oxidation, and alignment between metal wires and contacts, especially when using subtractive etching methods for 18-pitch metal gates.
Innovation Solution
A semiconductor device design with a gate electrode and contact plug structure that includes a gate extension portion and a gate contact protruding from the gate electrode, along with a method of manufacturing a semiconductor device, involving the formation of insulating films and metal layers to create a robust and aligned metal wire connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper damascene method is used for 18-pitch metal gate, then adhesion is secured, but resistance increases and copper filling margin is reduced
Solution Approach 1:
The patent segments the metal gate structure into multiple components: the main gate electrode, gate extension portions extending from the gate electrode, and gate contacts protruding from the gate extension portions. This segmentation allows each component to be optimized independently - the gate extension portions provide adequate copper filling margin while the gate contacts ensure proper adhesion and alignment with source/drain contacts, resolving the contradiction between adhesion and copper filling margin.
2Reliability
If adhesive layer is added to secure adhesion, then adhesion is improved, but resistance increases and residues are generated
Solution Approach 1:
The patent designs the gate extension portions and gate contacts with inherent adhesion properties through material selection and surface treatment, eliminating the need for separate adhesive layers. The gate contacts are formed with surfaces that naturally adhere to source/drain contacts, and the gate extension portions provide sufficient surface area for bonding. This self-service approach to adhesion avoids the resistance increase and residue generation associated with additional adhesive layers.
Data Source
AI summary
A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction that intersects with the first direction on the substrate, a source/drain pattern on the active pattern, a contact plug spaced apart from the gate electrode in the first direction, an insulating layer on the gate electrode and the contact plug, a first metal layer on the gate electrode in a first hole extending through the insulating layer in a third direction that intersects with the first direction and the second direction, a second metal layer on the contact plug in a second hole extending through the insulating layer in the third direction, a first metal wire on the first metal layer and the insulating layer, and a second metal wire on the second metal layer and the insulating layer.