Gate Contact Layout with Dielectric Cut Isolation in Tight S/D Spacing
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Solution Overview
Problem
Conventional methods for forming gate contacts in semiconductor devices face challenges due to tight spacing between source/drain contacts, leaving insufficient room for gate contact formation, especially as transistors are scaled down for increased density.
Innovation Solution
A semiconductor structure is developed with a dielectric contact cut between source/drain contacts of neighboring transistors, where the top surface of the dielectric contact cut is coplanar with a dielectric gate cap, allowing for easier formation of a gate contact that is separated from the contact cut by a gate spacer, and positioned in an extension along the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dielectric contact cut is used to separate tightly spaced source/drain contacts, then spacing between neighboring transistors is improved, but room for forming gate contact over source/drain region is reduced
Solution Approach 1:
The patent introduces a vertical dimension by forming the gate contact at a higher elevation than the source/drain contacts. The gate contact is positioned above the dielectric contact cut level, utilizing the third dimension (height) to resolve the horizontal spacing constraint. This allows tight in-plane spacing while maintaining adequate separation through vertical stratification of different contact types.
Solution Approach 2:
The patent introduces an intermediary dielectric layer that fills the gate contact opening and extends down to the dielectric contact cut. This intermediary dielectric material acts as a mediator between the gate contact and the underlying dielectric contact cut, providing both structural support and electrical isolation, enabling the gate contact to be formed in the extended direction without directly interfering with the source/drain contact separation.
2Productivity
If transistors are scaled down for increased device density, then device density is improved, but tight tip-to-tip distance between metal contacts is worsened
Solution Approach 1:
The patent applies vertical dimensionality to maintain adequate contact spacing while scaling horizontally. By positioning the gate contact above the dielectric contact cut and using the extended direction along the gate structure, the design achieves reduced in-plane footprint without compromising the tip-to-tip distance between source/drain contacts, thus enabling higher device density while maintaining manufacturability.
3Ease of manufacture
If gate contact is formed in the extension of dielectric contact cut, then alignment and spacing for manufacturing is improved, but risk of affecting dielectric contact cut during formation is increased
Solution Approach 1:
The patent uses an intermediary dielectric layer that fills the gate contact opening and extends down to the dielectric contact cut. This intermediary layer provides mechanical support during gate contact formation and ensures that the gate contact etching process does not directly expose or damage the underlying dielectric contact cut. The intermediary dielectric acts as a protective buffer, allowing alignment in the extended direction while preserving the integrity of the original contact cut.
Solution Approach 2:
The patent performs preliminary action by forming the dielectric contact cut and filling it with dielectric material before forming the gate contact. This sequence ensures that the dielectric contact cut is established and protected before the gate contact formation process begins, reducing the risk of accidental damage during subsequent processing steps.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dielectric contact cut between a first source/drain contact of a first transistor and a second source/drain contact of a second transistor; a gate structure shared by the first and the second transistor; and a gate cap on top of the gate structure, where a top surface of the dielectric contact cut is substantially coplanar with a top surface of the gate cap and substantially coplanar with top surfaces of the first S/D contact and the second S/D contact. A method of forming the same is also provided.