Gate Contact Opening Etch Profile Control Using Doped Dielectric Caps
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Solution Overview
Problem
The depth loading issue during the formation of gate contact openings in integrated circuit fabrication leads to uneven etching, resulting in increased risk of leakage current and contact resistance due to inaccuracies in the etching process, causing wider openings to punch through etch stop layers and narrower openings to have tapered profiles.
Innovation Solution
An additional ion implantation step is performed on the gate dielectric caps to create doped regions with different etch selectivity, slowing down the liner removal etching process and preventing tiger-tooth like patterns, thereby ensuring more vertical contact openings and increased contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used for gate contact openings, then etching speed is maintained, but etching uniformity deteriorates due to depth loading effect
Solution Approach 1:
The patent applies local quality by doping specific regions of the gate dielectric cap with different dopant concentrations. The first doped region has a first dopant concentration while the second doped region has a second dopant concentration, creating localized variations in etch resistance. This allows the etching process to proceed at different effective rates in different areas, compensating for the depth loading effect and achieving uniform etching across contacts of varying depths without sacrificing overall etching speed.
Solution Approach 2:
The patent changes the physical-chemical parameters of the gate dielectric cap by introducing dopants with different concentrations. The dopant concentration becomes a spatially varying parameter that controls the etch rate locally. By adjusting dopant concentration in different regions, the patent transforms the uniform etching problem into a controlled differential etching process that maintains both speed and uniformity.
2Manufacturing precision
If etching process continues to remove material, then contact opening depth increases, but leakage current risk increases due to punched through etch stop layers
Solution Approach 1:
The patent applies preliminary action by pre-doping the gate dielectric cap with regions of different dopant concentrations before the etching process begins. The first doped region with higher dopant concentration is positioned to resist etching when the contact opening reaches a critical depth. This pre-established dopant distribution acts as a built-in depth control mechanism that prevents over-etching and punching through of etch stop layers, thereby maintaining reliability while achieving precise depth control.
Solution Approach 2:
The dopant-concentration-gradient acts as a feedback mechanism during etching. As the etch front progresses through the gate dielectric cap, it encounters regions of varying dopant concentration that modulate the etch rate. The higher dopant concentration regions provide increased etch resistance that automatically slows down the etching process, preventing excessive depth and potential damage to underlying layers, thus providing self-regulating depth control.
3Productivity
If etching process is accelerated, then productivity improves, but contact opening profile deteriorates with increased tapering
Solution Approach 1:
The patent uses local quality by creating dopant concentration gradients within the gate dielectric cap. The dopant concentration varies spatially, with higher concentrations positioned to counteract tapering effects. This localized dopant distribution creates regions of differential etch resistance that compensate for the natural tapering tendency of high-speed etching processes, maintaining vertical profiles even at increased etching speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of leakage current and decreases contact resistance by maintaining a more vertical profile and increasing the gate contact area, effectively addressing the depth loading issue and improving the reliability of the integrated circuit structure.
Implementation Method 1
an additional ion implantation step is performed on the gate dielectric caps to create doped regions
Data Source
AI summary
The present disclosure includes an ion implantation step that creates doped regions in gate dielectric caps. The doped regions have a different material composition and hence a different etch selectivity than un-doped regions in the gate dielectric caps. The doped regions thus allow for slowing down a subsequent etching process of forming gate contact openings.