Gate Contact Filling for High-Aspect-Ratio Semiconductor Openings

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Solution Overview

Problem

The challenge in semiconductor manufacturing lies in filling high aspect ratio openings with conductive materials while minimizing defects such as voids, which affects contact resistance and device performance.

Innovation Solution

A selective deposition process is used to form a first conductive material at the bottom surfaces of openings, reducing the aspect ratio and facilitating gap-filling with a second conductive material, thereby minimizing void formation and improving contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional filling processes are used for high aspect ratio openings, then the openings can be filled with conductive material, but voids and defects form during filling

Engineering Contradiction:
Improvefilling qualityVSAvoiddefect rate
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A liner layer is formed at the bottom of high aspect ratio openings before the main conductive material is deposited. This preliminary action creates a foundation that facilitates complete gap-filling and prevents void formation during subsequent material deposition, thereby improving filling quality and reducing defects

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner layer acts as an intermediary between the opening structure and the main conductive material. It mediates the filling process by providing a surface that enables complete material deposition, ensuring reliable electrical connectivity without voids or defects

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If high aspect ratio openings are filled with conductive material, then electrical connectivity is achieved, but contact resistance increases due to voids and defects

Engineering Contradiction:
Improveelectrical connectivityVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The liner layer is deposited at the bottom of openings before the main conductive material, creating a defect-free foundation that ensures low contact resistance. This preliminary structure prevents void formation that would otherwise increase resistance and degrade electrical connectivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner layer provides localized quality enhancement at the critical bottom region of high aspect ratio openings. By concentrating the preventive action where voids most commonly form, the structure ensures uniform conductive material deposition and maintains low contact resistance throughout the electrical pathway

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces defects and enhances the performance of semiconductor devices by ensuring effective filling of high aspect ratio openings, leading to improved electrical connectivity and reduced resistance.

Implementation Method 1

A selective deposition process is used to form a first conductive material at the bottom surfaces of openings

Methodology Applied
Scientific EffectSelective deposition: Physical Vapour Deposition

Data Source

PatentUS20250254907A1Semiconductor structure and method of forming the same
Publication Date: 2025.08.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250254907A1 patent drawing
  • US20250254907A1 patent drawing
  • US20250254907A1 patent drawing

AI summary

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.