Self-Aligned Gate Contact Structure for IC Interconnect Reliability
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Solution Overview
Problem
As feature sizes in integrated circuits shrink, it becomes challenging to provide reliable source, drain, and gate contacts in middle-of-line interconnections due to increased contact resistance and misalignment issues, leading to potential shorting and area inefficiencies.
Innovation Solution
The solution involves a bottom-up formation of gate contacts to prevent misalignment and a top-down formation of source-drain contacts with sufficient size to reduce resistance and prevent shorting, using high K and low K materials for improved reliability and density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate contact is moved away from active area to avoid shorting, then shorting between gate contact and trench silicide is avoided, but chip area increases
Solution Approach 1:
The patent merges the gate contact formation with the source-drain contact formation by using a common contact opening etch process. The gate contact and source-drain contacts are formed simultaneously in the same etch step, eliminating the need to move the gate contact away from the active area and reducing overall chip area while maintaining reliability
2Area of stationary object
If merged fin structure and shared source-drain structures are used, then chip area is reduced, but contact resistance increases due to reduced contact area
Solution Approach 1:
The patent applies local quality by forming contacts with different dimensions in the same etch process. Source-drain contacts are formed with larger openings to reduce contact resistance, while gate contacts are formed with smaller openings. The contact opening size is locally optimized for each contact type, allowing area reduction through merged structures while maintaining low contact resistance through sufficient contact area
3Ease of manufacture
If conventional top-down contact formation is used, then manufacturing is simpler, but misalignment between gate and gate contact occurs leading to shorting
Solution Approach 1:
The patent uses self-aligned contact formation where the contact opening is defined by the sidewall spacers of the gate structure. The etch process automatically aligns the gate contact with the gate electrode through the physical presence of the spacers, eliminating misalignment issues while maintaining manufacturing simplicity. The process is self-correcting, as any deviation from alignment is prevented by the spacer geometry
Data Source
AI summary
An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.