Gate Contact Structure With Insulating Spacer For Transistor

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Solution Overview

Problem

The existing methods for forming gate contact structures in integrated circuits are complex and inefficient, leading to increased costs and reduced yields, particularly when attempting to position the gate contact entirely over the active region without causing electrical shorts.

Innovation Solution

A method involving the formation of a gate contact structure that includes a conductive source/drain metallization structure with an internal insulating spacer, allowing for the exposure of the gate structure while maintaining electrical coupling, thereby reducing the complexity and increasing the packing density without the need for additional process steps or materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate contact structure is formed using existing methods to position it entirely over the active region, then electrical short prevention is improved, but the process complexity increases and manufacturing yield decreases

Engineering Contradiction:
Improveelectrical short preventionVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate contact structure is divided into multiple segments: a first gate contact portion extending from the gate electrode through the first interlayer dielectric layer, and a second gate contact portion extending from the gate electrode through the second interlayer dielectric layer. This segmentation allows each portion to be independently formed and positioned, enabling the gate contact to be entirely over the active region while using standard process steps, thus reducing overall process complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate contact structure extends in the vertical dimension through multiple interlayer dielectric layers, with the first gate contact portion and second gate contact portion positioned at different heights. This three-dimensional arrangement allows the gate contact to be entirely over the active region without requiring complex lateral positioning, simplifying the manufacturing process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the gate contact structure is formed using existing methods with additional process steps, then electrical short prevention is improved, but manufacturing cost increases

Engineering Contradiction:
Improveelectrical short preventionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The gate contact structure utilizes the existing gate electrode and standard interlayer dielectric layer formation processes to define its position and structure. The first and second gate contact portions are formed using常规 deposition and etching steps that are already part of the manufacturing process, eliminating the need for additional specialized process steps and reducing manufacturing cost.

Inventive Principle:
Principle #25Self-service

3Device complexity

If the gate contact structure is formed using existing methods, then manufacturing process is simpler, but space utilization on the integrated circuit is reduced

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidspace utilization
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The gate contact structure utilizes the vertical dimension by extending through multiple interlayer dielectric layers with the first gate contact portion and second gate contact portion positioned at different heights. This three-dimensional configuration allows the gate contact to be entirely over the active region, maximizing space utilization on the integrated circuit while maintaining manufacturing process simplicity using standard process steps.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11621333B2Gate contact structure for a transistor device
Publication Date: 2023.04.04 GLOBALFOUNDRIES US INC
  • US11621333B2 patent drawing
  • US11621333B2 patent drawing
  • US11621333B2 patent drawing

AI summary

One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.