Gate Contact Layout for Non-Planar Transistors
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Solution Overview
Problem
Modern semiconductor manufacturing faces challenges with short channel effects, capacitive coupling, electro migration, leakage currents, and complex processing steps when designing non-planar transistors, which affect yield and time to market.
Innovation Solution
The method involves placing gate contacts outside the active region of non-planar vertical conducting structures, using a less complex fabrication process, and forming gate extension contacts above the active regions to connect gate metal to interconnect layers, reducing the height of the cell layout and improving scalability and metal track routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate contacts are placed over active regions in non-planar devices, then manufacturing complexity is reduced, but short channel effects increase
Solution Approach 1:
The gate contact structure is segmented into two distinct parts: (1) a first gate contact extending from the gate metal to the interconnect layer, and (2) a second gate contact extending from the gate metal to the interconnect layer. This segmentation allows the gate contacts to be positioned outside the active region while maintaining electrical connection, thereby reducing manufacturing complexity without exacerbating short channel effects.
Solution Approach 2:
The gate contacts are extended vertically in the z-dimension to reach from the gate metal layer up to the interconnect layer, rather than being confined to the planar x-y plane. This dimensional extension enables the gate contacts to be positioned outside the active region footprint, simplifying the fabrication process while avoiding short channel effect degradation.
2Productivity
If contact placement is flexible in standard cell layout, then scaling and metal routing improve, but yield reduces due to short circuits
Solution Approach 1:
The gate contacts are preliminarily positioned outside the active region during the layout design phase, with their locations predetermined to avoid potential short circuit paths. This preliminary positioning allows flexible contact placement for improved scaling and metal routing while maintaining yield by preventing short circuits before fabrication occurs.
Solution Approach 2:
The gate metal layer acts as an intermediary element that connects the gate contacts (positioned outside the active region) to the transistor gate. This intermediary structure enables flexible contact placement while maintaining reliable electrical connection, thereby improving scaling and routing without compromising yield.
3Reliability
If contact placement flexibility is reduced to prevent short circuits, then yield improves, but standard cell size increases and metal tracks decrease
Solution Approach 1:
Instead of placing gate contacts inside the active region (conventional approach), the invention inverts the placement strategy by positioning gate contacts outside the active region. This inversion maintains yield by preventing short circuits while actually reducing standard cell size, as the contacts no longer occupy valuable active region space.
Solution Approach 2:
The gate contacts utilize the vertical dimension (z-axis) to extend from the gate metal layer to the interconnect layer, freeing up horizontal space in the standard cell layout. This dimensional utilization allows yield improvement through restricted contact placement while preventing standard cell size increase.
Data Source
AI summary
A system and method for laying out power grid connections for standard cells are described. In various implementations, gate metal is placed over non-planar vertical conducting structures, which are used to form non-planar devices (transistors). Gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts. Gate extension contacts are formed on the GEM above the active regions. Similar to gate contacts, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region.