Gate Contact Plug Protrusion Reducing Semiconductor Resistance
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to achieve high performance and integration while minimizing resistance between conductive structures, which existing technologies have not adequately addressed, leading to suboptimal electrical characteristics and reliability.
Innovation Solution
The semiconductor device incorporates a substrate with defined regions, including a cell array, peripheral circuit, and connection regions, featuring a gate structure with a gate electrode and a gate contact plug. The gate contact plug has a protrusion extending along the end surface of the gate electrode, and includes multiple insulating layers, enhancing contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact technologies are used to connect conductive structures, then device integration is achieved, but resistance between adjacent conductive structures remains high
Solution Approach 1:
The gate contact plug transitions from a conventional planar contact to a three-dimensional structure with a protrusion extending downward along the end surface of the gate electrode. This vertical extension into the device separation layer creates additional contact area in the depth dimension, reducing contact resistance between the gate contact plug and gate electrode.
Solution Approach 2:
The gate contact plug is embedded within the device separation layer, with the protrusion nested between the end surface of the gate electrode and the insulating liner. This nested configuration allows the contact plug to achieve intimate contact with the gate electrode while being surrounded and supported by the device separation structure.
2Productivity
If device scaling is pursued to achieve higher integration, then miniaturization is achieved, but contact resistance between conductive structures increases
Solution Approach 1:
As devices scale down, the contact interface area in the planar dimension decreases. The protrusion structure compensates for this by extending vertically along the gate electrode end surface, maintaining adequate contact area despite reduced lateral dimensions. This enables continued scaling while preserving electrical performance.
Solution Approach 2:
The device separation layer provides localized electrical isolation around the gate contact plug protrusion, ensuring that the reduced contact resistance at the gate interface does not compromise adjacent device performance. This localized quality control allows aggressive scaling while maintaining overall device reliability.
Data Source
AI summary
A semiconductor device includes a substrate having a cell array region, a peripheral circuit region, and a connection region, a device separation region including a first device separation layer defining a cell active region on the cell array region, a second device separation layer defining a peripheral active region on the peripheral circuit region, and a third device separation layer defining an active dam on the connection region, a gate structure including a gate electrode crossing the cell active region on the cell array region, extending into the third device separation layer on the connection region, and having an end surface in the third device separation layer, and a gate contact plug electrically connected to the gate electrode on the connection region, wherein the third device separation layer includes a first insulating liner, a second insulating liner on the first insulating liner, and an embedded insulating layer.