Gate Contact Recesses Prevent Etch-Through in HKMG Devices
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Solution Overview
Problem
High-k metal gate (HKMG) devices face challenges such as increased complexity in device fabrication due to additional layers, which can lead to power short circuits during contact etching, particularly in analog devices with thicker gate dielectric layers.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with recesses in the isolation structure to accommodate a thicker metal fill layer under the gate contact, reducing the risk of etch-through and electrical shorts by maintaining a sufficient thickness of the metal fill layer over recesses in the isolation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional layers are added to the gate structure to achieve high-k metal gate functionality, then the gate dielectric performance is improved, but the device fabrication complexity increases and the metal layer thickness is reduced
Solution Approach 1:
The patent introduces a recess in the isolation structure at a specific location beneath the gate contact, creating a localized structural modification. This recess provides additional space for the metal fill layer only where needed, without requiring additional layers across the entire gate structure. The selective local modification resolves the contradiction by improving metal layer thickness at the contact point while maintaining the overall gate dielectric performance.
2Reliability
If the gate dielectric layer is made thicker to improve device performance, then the gate insulation is enhanced, but the metal fill layer thickness is reduced increasing etch-through risk
Solution Approach 1:
The patent solves the thickness conflict by transitioning from a two-dimensional planar structure to a three-dimensional structure with a recess. The recess creates vertical space beneath the gate contact, allowing the metal fill layer to maintain sufficient thickness even when the gate dielectric layer is thickened. This dimensional change enables both improved gate insulation and adequate metal layer thickness to prevent etch-through.
3Ease of manufacture
If standard contact etching is performed through the gate stack, then the gate contact is formed, but power short circuits occur due to insufficient metal fill layer thickness
Solution Approach 1:
The recess in the isolation structure is formed beforehand, before the contact etching process. This preliminary structural preparation ensures that when the contact etch is performed later, the metal fill layer already has sufficient thickness at the contact location, preventing power short circuits. The advance preparation of the recessed structure eliminates the need for process adjustments during contact formation.
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.