Gate Contact Resistance Reduction via Segregation Layer
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Solution Overview
Problem
Existing high-K/metal gate stacks in semiconductor devices suffer from increased gate contact resistance due to native oxide layers, which limits device performance and scaling, as current techniques like pre-doping and increased source/drain doping only provide partial reductions in alternating current resistance.
Innovation Solution
A method involving the formation of a segregation layer with impurities between the metal gate electrode and the gate contact layer, achieved through impurity implantation and subsequent annealing, to reduce the Schottky barrier height and gate contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If native oxide layer is present at the a-Si/metal interface, then the gate stack structure is naturally formed, but gate contact resistance and AC Reff increase
Solution Approach 1:
An impurity layer (such as nitrogen, carbon, or silicon-rich layer) is introduced as an intermediary between the metal gate electrode and the a-Si gate contact layer. This intermediate layer reduces the Schottky barrier height at the metal-semiconductor interface, thereby reducing gate contact resistance and AC Reff without requiring complete elimination of the native oxide layer.
Solution Approach 2:
The Schottky barrier height at the metal-a-Si interface is modified by changing the chemical composition and electronic structure through impurity layer formation. This parameter change (reducing barrier height) directly reduces the contact resistance while maintaining the natural oxide layer structure.
2Reliability
If pre-doping or increased S/D doping is used to reduce gate contact resistance, then AC Reff decreases by about 150-200 ohms, but the doping concentration at the a-Si/metal interface remains insufficient
Solution Approach 1:
An impurity layer is formed preliminarily between the metal gate and a-Si layer before final device operation. This preliminary action ensures high impurity concentration is already present at the critical interface region, eliminating the need for relying solely on diffusion from source/drain regions and achieving better contact resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases gate contact resistance and alternating current resistance, thereby improving device performance by minimizing impurity diffusion and achieving high impurity concentration at the interface, leading to reduced series contact resistance.
Implementation Method 1
an anneal process is performed to convert the impurity layer into a segregation layer
Implementation Method 2
Current techniques developed by one or more of the inventors for reducing SBH at the S/D contacts employ impurity segregation at the silicide/semiconductor (e.g., NiSi/Si) interface
Data Source
AI summary
A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.