Gate Contact Opening Profile Control via Sidewall Oxidation
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Solution Overview
Problem
The existing methods for forming gate contacts in integrated circuit structures, particularly in FinFETs and GAA transistors, face challenges such as increased risk of leakage current due to lateral etching during the formation of gate contact openings, which can lead to bowing profiles and compromised device performance.
Innovation Solution
An additional plasma treatment for sidewall oxidation on the middle contact etch stop layer (MCESL) and gate dielectric caps is introduced, creating regions with different etch selectivity to inhibit lateral etching, thereby reducing the risk of leakage current and maintaining a bowing-free profile in the gate contact openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching methods are used to form gate contact openings, then the etching process can be completed, but lateral etching occurs causing bowing profiles and increased leakage current risk
Solution Approach 1:
The patent applies different etch selectivity to different regions by introducing sidewall oxidation on the MCESL and gate dielectric caps. This creates a non-uniform surface where oxidized sidewalls have different etching characteristics compared to non-oxidized regions, thereby controlling lateral etching and preventing bowing profiles while maintaining overall etching productivity.
Solution Approach 2:
The patent changes the physical-chemical state of the MCESL and gate dielectric cap sidewalls through oxidation treatment. This parameter change (from non-oxidized to oxidized state) modifies the etch selectivity of these regions, enabling differential etching rates that control the gate contact opening profile and eliminate bowing while maintaining etching efficiency.
2Device complexity
If etching is performed without sidewall oxidation, then the process is simpler, but leakage current risk increases due to lateral etching and bowing profiles
Solution Approach 1:
The patent performs sidewall oxidation as a preliminary action before the etching process. By pre-oxidizing the sidewalls of the MCESL and gate dielectric caps, the patent creates a protective layer with different etch selectivity that prevents lateral etching during the subsequent etching step. This preliminary action ensures reliable gate contact opening formation without leakage current, with the added complexity being justified by the significant reliability improvement.
3Speed
If lateral etching is not inhibited, then the etching process is faster, but the distance between gate contacts and source/drain contacts decreases causing performance compromise
Solution Approach 1:
The patent creates local quality differences through selective sidewall oxidation on the MCESL and gate dielectric caps. The oxidized sidewalls exhibit different etch selectivity compared to non-oxidized areas, enabling the etching process to proceed vertically at high speed while lateral etching is inhibited at the critical interfaces. This maintains both fast etching rates and precise gate contact positioning with adequate separation from source/drain contacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The sidewall oxidation treatment effectively slows down lateral etching, reducing the risk of leakage current and ensuring a bowing-free geometry for the gate contacts, which enhances the reliability and performance of the integrated circuit structures by maintaining a larger distance from source/drain contacts.
Implementation Method 1
An additional plasma treatment for sidewall oxidation on the middle contact etch stop layer (MCESL) and gate dielectric caps is introduced
Implementation Method 2
An additional plasma treatment for sidewall oxidation on the middle contact etch stop layer (MCESL) and gate dielectric caps is introduced
Data Source
AI summary
A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.