Spacer-Isolated Gate Contact Structure to Prevent Leakage
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Solution Overview
Problem
Existing semiconductor devices suffer from short circuit and leakage issues due to the lack of isolation between conductive structures, leading to poor performance and limited application.
Innovation Solution
A fabrication method that forms a second groove and a spacer on its sidewalls, isolating the second conductive structure from the first conductive structure, thereby preventing short circuits and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are placed close together to increase device density, then device integration level is improved, but short circuit and leakage occur between conductive structures
Solution Approach 1:
A dielectric layer is introduced as an intermediary substance between adjacent conductive structures (first conductive structure and second conductive structure). This dielectric layer acts as an insulating barrier that prevents electrical short circuits and leakage currents while allowing the conductive structures to be placed in close proximity, thereby maintaining high device density without compromising reliability.
2Reliability
If isolation structures are added between conductive structures to prevent short circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The dielectric layer serving as an isolation structure is merged with the interlayer dielectric structure that already exists in the semiconductor device architecture. By integrating the isolation function into the existing dielectric layer rather than adding a separate isolation structure, the patent prevents short circuits between conductive structures while minimizing increases in device complexity.
3Ease of manufacture
If conventional planar devices are used, then manufacturing is simple, but control capability on channel current becomes weak resulting in short channel effect
Solution Approach 1:
The patent transitions from a conventional planar (two-dimensional) device architecture to a three-dimensional structure by stacking conductive structures vertically with dielectric layers in between. This dimensional change enables better control of channel current through the vertical field effect while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a base substrate; a gate structure on the base substrate; source/drain doped layers in the base substrate on sides of the gate structure; a first dielectric layer on the base substrate and covering the source/drain doped layers; a mask layer on a top of the gate structure between the source/drain doped layers; a second dielectric layer on the first dielectric layer and exposing a surface of the mask layer; first grooves in the second dielectric layer and the first dielectric layer, and exposing the source/drain doped layers; a first conductive structure in each first groove; a second groove in the mask layer, and exposing the gate structure at a bottom of the second groove; and a spacer on sidewalls of the second groove.