Gate-to-Contact Via-First Structure for Low-Resistance IC Interconnects
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Solution Overview
Problem
The integrated circuit (IC) manufacturing process faces challenges in forming gate-to-contact (GC) structures due to exposure of the source/drain region during etching, leading to oxide formation and increased contact resistance, as well as stringent overlay and dimension control requirements for high-density MOL interconnects, which can result in leakage current and electrical shorting.
Innovation Solution
A via-first process is employed to electrically couple an active region (AR) contact and a gate electrode, where an etch stop layer and additional ILD layers are used to form openings with a slanted bottom, allowing for a metal layer deposition with reduced aspect ratio and risk of seams or voids, thereby relaxing overlay and dimension control constraints and preventing oxidation of the source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching process is used to form GC structures, then gate contact can be formed, but source/drain region is exposed leading to oxide formation and increased contact resistance
Solution Approach 1:
The patent applies preliminary action by forming the via opening to the gate electrode before forming the contact opening to the source/drain region. This sequence allows the via to be filled with metal first, creating a protective structure that prevents oxide formation on the source/drain region during subsequent processing steps.
Solution Approach 2:
The patent introduces an intermediary metal layer (the via fill material) between the etching process and the source/drain region. This metal via acts as a mediator that protects the source/drain region from direct exposure to oxidizing environments while still allowing electrical connection to be established.
2Productivity
If high-density MOL interconnects are formed with stringent overlay and dimension control, then routing density increases, but leakage current and electrical shorting occur
Solution Approach 1:
The patent segments the GC structure into distinct components: a via portion extending to the gate electrode and a contact portion extending to the source/drain region. This segmentation allows each portion to be optimized independently for its specific function while maintaining adequate spacing to prevent leakage current between adjacent structures.
Solution Approach 2:
The patent applies local quality by giving different portions of the GC structure different characteristics. The via portion has dimensions optimized for aligning with the gate electrode, while the contact portion has dimensions optimized for connecting to the source/drain region. This localized optimization allows high routing density while preventing electrical shorting through inappropriate dimensional constraints applied uniformly across the entire structure.
3Manufacturing precision
If metal layer with high aspect ratio is deposited, then via filling can be achieved, but seams and voids form reducing structure robustness
Solution Approach 1:
The patent changes the geometric parameters of the via opening by controlling its width and depth ratio (aspect ratio) to enable complete metal filling without forming seams or voids. By optimizing the via dimensions within acceptable ranges, the metal layer can be deposited continuously across the via, creating a robust filled structure rather than a fragmented one with defects.
Data Source
AI summary
Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.