Gate Contact Void Structure for Lower FinFET Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, the formation of air gaps or voids between gate structures and source/drain regions during the process of forming contacts to transistors leads to increased parasitic capacitance, affecting the performance of FinFETs.
Innovation Solution
The removal of gate spacers during the process of forming contacts to the gate structures of transistors results in air gaps or voids with low relative permittivity, reducing parasitic capacitance and improving the performance of FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If gate spacers are removed during contact formation, then parasitic capacitance is reduced due to air gaps, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The gate spacer is removed before contact formation to create air gaps that reduce parasitic capacitance. This preliminary removal action enables subsequent contact openings to be formed with improved electrical performance while maintaining manufacturing control through the self-aligned nature of the process
Solution Approach 2:
The air gap created by gate spacer removal acts as an intermediary layer between the gate structure and source/drain contacts. This intermediate air region provides electrical isolation that reduces parasitic capacitance while allowing the contact formation process to proceed with controlled precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduction of parasitic capacitance enhances the performance of FinFETs by minimizing electrical interference and improving overall device efficiency.
Implementation Method 1
The removal of gate spacers during the process of forming contacts to the gate structures of transistors leads to increased parasitic capacitance, affecting the performance of FinFETs
Implementation Method 2
The removal of gate spacers during the process of forming contacts to the gate structures of transistors results in air gaps or voids with low relative permittivity, reducing parasitic capacitance
Data Source
AI summary
In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.