Gate Control Chip for Display Module Signal Reliability

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Solution Overview

Problem

The risk of abnormal operation of the Gate Driver on Array (GOA) circuit due to short circuits among the wirings for transmitting GOA control signals is high, leading to reduced yield in display panel manufacturing.

Innovation Solution

A display module with a gate control chip having a first and second output pin, both electrically connected to the gate driving circuit, where the chip controls the second output pin to output a signal when the first signal is abnormal and prevents the first output pin from outputting the signal, thereby avoiding abnormal operation of the gate driving circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the gate driving circuit is disposed in the non-display area with multiple wirings for GOA control signals, then the border of the display screen can be narrowed, but the risk of short circuit among wirings increases and the yield is reduced

Engineering Contradiction:
Improveborder widthVSAvoidcircuit operation reliability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent introduces a gate control chip as an intermediary component between the signal source and the gate driving circuit. This chip provides multiple output pins (first output pin and second output pin) that are both electrically connected to the gate driving circuit, serving as a mediator to deliver control signals and reduce wiring complexity on the array substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate control chip is configured with abnormal signal detection and backup output capabilities. When the first signal from the first output pin is detected as abnormal, the chip automatically switches to output through the second output pin, providing beforehand cushioning against potential failures and ensuring continuous operation of the gate driving circuit.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Device complexity

If multiple wirings are disposed on the array substrate to transmit GOA control signals, then the gate driving circuit can be integrated, but the wirings become excessively close and short circuits occur

Engineering Contradiction:
Improvecircuit integrationVSAvoidshort circuit risk
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The gate control chip acts as an intermediary that consolidates multiple signal output functions in a single component. By providing multiple output pins on the chip itself, it reduces the need for multiple separate wirings on the array substrate, thereby decreasing wiring density and short circuit risk while maintaining circuit integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions the signal output functionality from the substrate plane (multiple wirings) to a vertical dimension (multiple output pins on a three-dimensional chip structure). This dimensional change allows multiple signals to be delivered through a compact component rather than spread out as separate wirings, reducing spatial interference and short circuit risk.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12148338B2Display module including gate control chip and electronic terminal including the same
Publication Date: 2024.11.19 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US12148338B2 patent drawing
  • US12148338B2 patent drawing
  • US12148338B2 patent drawing

AI summary

The present disclosure provides a display module and an electronic terminal. The display module includes a panel including a display area and a non-display area on at least one side of the display area, where a gate driving circuit is disposed in the non-display area; and a gate control chip including a first output pin and a second output pin, where both the first output pin and the second output pin are electrically connected to the gate driving circuit, where, the gate control chip is configured to, when a first signal outputted from the first output pin is abnormal, control the second output pin to output a second signal, and control the first output pin not to output the first signal.