Gate Control Circuits for Simultaneous Scanning in Display Devices
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Solution Overview
Problem
In liquid crystal display devices, simultaneous scanning of adjacent gate lines results in display unevenness due to differences in gate on characteristics and insufficient writing time, leading to lateral stripes and performance issues.
Innovation Solution
A display device with gate control circuits that include first and second output terminals, allowing for simultaneous scanning of adjacent gate lines with synchronized gate on periods, and selector circuits to manage signal supply based on scanning mode, ensuring equal gate on characteristics and sufficient writing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If adjacent two gate lines are scanned simultaneously to improve scanning speed, then productivity is improved, but gate on characteristics become different and writing time becomes insufficient
Solution Approach 1:
The patent applies preliminary action by providing a gate on period before the simultaneous scanning of adjacent gate lines. During this gate on period, the outputs from the first output terminals of adjacent two gate control circuits are made the same, ensuring uniform gate on characteristics before the actual simultaneous scanning begins. This preliminary synchronization resolves the contradiction by preparing the system in advance to maintain uniformity while achieving high-speed simultaneous scanning.
2Loss of time
If adjacent two gate lines are scanned simultaneously to reduce writing time, then loss of time is reduced, but writing characteristics become unsaturated and display unevenness occurs
Solution Approach 1:
The gate on period serves as a preliminary action that ensures proper writing characteristics are established before simultaneous scanning. By making the outputs from the first output terminals of adjacent gate control circuits the same during this period, the system prepares the necessary conditions for successful writing, ensuring saturation of writing characteristics even when the overall writing time is reduced through simultaneous scanning.
Solution Approach 2:
The patent employs periodic action by structuring the scanning process with distinct periods: a gate on period where outputs are synchronized, followed by the simultaneous scanning period. This periodic structure allows the system to maintain reliable writing characteristics during the synchronized gate on period while achieving time efficiency during the simultaneous scanning period, thus resolving the contradiction between writing time and writing characteristics saturation.
3Productivity
If shift register connects every two cycles to enable simultaneous scanning, then productivity is improved, but gate on time interval appears and writing difference occurs
Solution Approach 1:
The gate on period acts as a preliminary action that compensates for the time interval issues introduced by the shift register's two-cycle connection. By synchronizing the outputs during this preliminary period, the system ensures that writing time consistency is maintained across adjacent gate lines even though the shift register connects every two cycles, thus enabling simultaneous scanning without writing differences.
Data Source
AI summary
There is provided a display device including an array substrate including pixels arranged in a matrix manner and gate control circuits that scan gate lines of the pixels and that are provided on the array substrate such that the gate control circuits correspond to the respective gate lines of the pixels. Each of the gate control circuits includes a first output terminal that outputs a signal to each of the gate lines, and a second output terminal that outputs a signal that is supplied to a gate control circuit in a subsequent stage. When adjacent two of the gate lines are scanned simultaneously from an upper part of a screen by the signal output from the first output terminal of each of the gate control circuits, a gate on period is provided during which outputs from the first output terminals of adjacent two of the gate control circuits are the same.