Gate Control Layer Undercutting Gate Dielectric for Transistor Leakage Reduction
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Solution Overview
Problem
As transistor gates are scaled down, the source and drain regions become closer, leading to weak gate control over the channel, resulting in undesired channel current leakage due to increased source/drain underlap, which is exacerbated at the 10 nm patterning node and below.
Innovation Solution
The deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions increases the effective electrical gate length by separating the heavily doped source and drain regions, thereby improving gate control and reducing underlap distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimensions of transistor gates are scaled down to support more transistors per area, then the transistor density increases, but the gate control over the channel weakens due to increased source/drain underlap
Solution Approach 1:
The source and drain regions are segmented into multiple layers: a lightly-doped first source/drain region, a heavily-doped second source/drain region, and an intermediate region between them. This segmentation allows the intermediate region to serve as a buffer that maintains gate control while accommodating the heavily-doped regions, thus resolving the contradiction between high transistor density and effective gate control.
Solution Approach 2:
Different doping concentrations are applied to different spatial regions: the first source/drain regions are lightly-doped, the intermediate region has moderate doping, and the second source/drain regions are heavily-doped. This local differentiation of doping quality enables each region to perform its specific function - the lightly-doped regions maintain gate control, while the heavily-doped regions provide good contact, resolving the gate control issue at scaled dimensions.
2Reliability
If the source and drain regions are heavily doped to improve contact, then the electrical contact improves, but the channel current leakage increases due to source/drain underlap
Solution Approach 1:
The source and drain structures are divided into multiple doped regions with the intermediate region acting as a separator between the heavily-doped second source/drain regions and the channel. This segmentation prevents the heavily-doped regions from directly overlapping with the channel, thereby reducing channel current leakage while maintaining good electrical contact through the heavily-doped second source/drain regions.
Solution Approach 2:
The intermediate source/drain region serves as an intermediary layer between the lightly-doped first source/drain regions and the heavily-doped second source/drain regions. This intermediate layer with moderate doping concentration acts as a buffer that prevents direct contact between the heavily-doped regions and the channel, thereby reducing channel current leakage while still allowing the heavily-doped regions to provide good electrical contact.
Data Source
AI summary
Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (Leff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (Xud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (Leff) and improves the control that the gate has over the channel.