Gate Control Line Segmentation for Display Clock Load Reduction
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Solution Overview
Problem
Display devices face issues with increased load on clock lines leading to signal delays, affecting gate driver operation and luminance uniformity, and are prone to water damage due to parasitic capacitance and insulation layer absorption.
Innovation Solution
A display device design featuring a gate control line with overlapping first and second gate control lines through an insulation layer, and a cathode auxiliary electrode with outgas holes to reduce load on clock lines and prevent water damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the display device increases, then the display area is enlarged, but the load on clock lines increases causing signal delays
Solution Approach 1:
The clock line is divided into multiple segments with different voltage levels. A first clock line transmits clock signals at a first voltage level, while a second clock line transmits clock signals at a second voltage level. This segmentation allows the system to handle larger display areas by distributing the clock signal transmission across multiple lines with optimized voltage levels, thereby reducing signal delays and maintaining reliability.
2Device complexity
If a single gate control line is used, then the structure is simple, but signal delays occur in large-sized devices
Solution Approach 1:
The gate control line is segmented into a first gate control line and a second gate control line that operate at different voltage levels. The first gate control line receives clock signals at a first voltage level, while the second gate control line receives clock signals at a second voltage level. This segmentation enables faster signal transmission across the gate driver by providing multiple parallel paths with optimized voltage levels, thereby improving transmission speed without excessively increasing structural complexity.
3Reliability
If the cathode auxiliary electrode overlaps the clock line, then the voltage supply is stable, but parasitic capacitance affects the low-level voltage
Solution Approach 1:
An insulation layer is introduced as an intermediary between the cathode auxiliary electrode and the clock line. This insulation layer reduces the parasitic capacitance formed between the cathode auxiliary electrode and the clock line, thereby minimizing the harmful effects of parasitic capacitance on the low-level voltage supplied to the cathode auxiliary electrode, while still maintaining stable voltage supply through the auxiliary electrode's extended structure.
4Ease of manufacture
If the insulation layer is exposed to air, then manufacturing is simplified, but water absorption damages the light emitting element
Solution Approach 1:
The insulation layer is designed as a thin film structure that is integrated within the display device's encapsulation system. This thin film insulation layer is protected by the device's encapsulation layers (such as the cathode electrode and encapsulation layers) from water and oxygen exposure, preventing water absorption and subsequent damage to the light emitting element, while still allowing for simplified manufacturing processes during the insulation layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces clock line loads, prevents abnormal gate driver operation and luminance issues, and minimizes the impact of parasitic capacitance on cathode auxiliary electrodes, ensuring stable voltage supply and protecting light-emitting layers from water damage.
Implementation Method 1
An insulation layer in the display device may absorb water when exposed to air
Implementation Method 2
the low-level voltage supplied to the cathode auxiliary electrode can be effected by a parasitic capacitance generated between the cathode auxiliary electrode and the clock line CL
Data Source
AI summary
Disclosed is a display device for decreasing a load of a clock line. The display device comprises: a display panel including a plurality of data lines and a plurality of gate lines, and a plurality of pixels in a display area, a gate driver disposed in a non-display area of the display panel and supplying gate signals to the plurality of gate lines, and a gate control line for supplying a gate control signal to the gate driver. The gate control line includes a first gate control line and a second gate control line overlapping the first gate control line with an insulation layer therebetween, the second gate control line being connected to the first gate control line through a first contact hole passing through the insulation layer.