Gate Control Circuit With Overcurrent Limiting for MOS Transistor Protection
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Solution Overview
Problem
Existing gate control circuits for power semiconductor elements, such as IGBTs, are prone to breakdown due to large currents flowing between the source and drain when defects like short-circuits occur between the drain and power supply or ground levels, leading to potential transistor breakdown.
Innovation Solution
A gate control circuit with a first and second pulse generator, along with corresponding gate controlling portions, that include overcurrent controlling mechanisms to manage the gate voltage of transistors, preventing currents from exceeding threshold values by using current detecting and converting portions, and delay devices to prevent simultaneous activation of high-side and low-side drivers, thereby preventing transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain of the high-side MOS transistor or low-side MOS transistor shorts out to ground or power supply level, then a large current flows between source and drain causing breakdown, but adding protection circuits increases device complexity
Solution Approach 1:
The patent applies preliminary action by implementing overcurrent controlling portions that proactively limit the gate voltage before excessive current can flow. The first and second overcurrent controlling portions continuously monitor and regulate the gate voltage of the high-side and low-side MOS transistors, preventing short-circuit currents before they cause breakdown, rather than reacting after a fault occurs.
Solution Approach 2:
The patent uses intermediary elements by introducing overcurrent controlling portions as mediator circuits between the gate control signals and the MOS transistor gates. These intermediary circuits include voltage limiting components that act as buffers, preventing direct transmission of excessive voltage that would cause harmful currents, thus protecting the transistors without requiring complex protection structures.
2Ease of operation
If resistors are used to connect the drain of high-side MOS transistor and low-side MOS transistor to the gate, then the gate can be controlled, but large currents still flow during short-circuit defects causing breakdown
Solution Approach 1:
The overcurrent controlling portions perform preliminary action by pre-limiting the gate voltage to safe levels before current flow occurs. By continuously regulating the gate voltage through voltage limiting circuits, the system prevents the conditions that would lead to excessive current flow during short-circuit defects, maintaining both ease of gate control and transistor reliability.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the gate voltage parameter within safe operating limits. The overcurrent controlling portions modify the voltage level parameter in real-time, ensuring it never exceeds thresholds that would cause harmful current flow, thus maintaining reliable operation while preserving control capability.
3Reliability
If delay devices are added to prevent simultaneous activation of high-side and low-side drivers, then flow-through currents are prevented, but device complexity increases
Solution Approach 1:
The delay devices implement preliminary action by introducing time delays to the gate control signals, ensuring that one MOS transistor is fully turned off before the other is activated. This preliminary timing adjustment prevents the simultaneous conduction that would cause flow-through currents, eliminating the need for more complex protection circuits.
Solution Approach 2:
The patent uses periodic action through delay devices that introduce controlled time intervals in the switching sequence of high-side and low-side MOS transistors. By creating a non-overlapping periodic switching pattern, the system prevents flow-through currents while maintaining simple circuit architecture, as the delay elements naturally enforce the required timing separation.
Data Source
AI summary
A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.