Gate Control Circuit for Drain Voltage Slew Rate Adjustment
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Solution Overview
Problem
Existing gate control circuits for switching transistors in power supply and inverter circuits face challenges in controlling the slew rate of the drain voltage, leading to increased switching losses due to the dependence on load current, temperature, and element variations, without a specific method to adjust the slew rate effectively.
Innovation Solution
A gate control circuit comprising a transition time detection circuit, an error detection circuit, and a transition time control circuit that adjusts the gate drive signal to control the slew rate of the drain voltage by detecting the transition time and generating error voltage to synchronize the second pulse signal with the first pulse signal, allowing for precise control of the gate voltage and slew rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a resistor is inserted in series into the gate terminal to decrease the gate voltage change and suppress the slew rate of the drain voltage, then noise is reduced, but switching loss increases
Solution Approach 1:
The patent applies dynamics by making the gate resistance variable rather than fixed. The gate control circuit dynamically adjusts the gate resistance based on detected drain voltage slew rate, allowing the system to optimize between noise suppression and switching efficiency under different operating conditions. This resolves the contradiction by enabling the gate resistance to adapt: higher resistance when noise suppression is needed, and lower resistance when switching speed is prioritized.
Solution Approach 2:
The patent changes the parameter of gate resistance from a static value to a dynamically adjustable parameter. By controlling the gate resistance value based on the detected slew rate and comparing it with a target value, the system can adjust the gate voltage change rate to achieve optimal performance. This parameter change allows the system to balance noise suppression and switching loss reduction.
2Object-generated harmful factors
If the gate resistance is set to a value that ensures noise does not exceed a predetermined value under any operating conditions, then noise suppression is guaranteed, but the slew rate becomes significantly smaller than the predetermined value in many periods, causing unnecessary switching loss
Solution Approach 1:
The patent implements feedback by detecting the actual slew rate of the drain voltage and using this information to adjust the gate resistance. The gate control circuit continuously monitors the slew rate and compares it with a target value, then adjusts the gate resistance accordingly. This closed-loop feedback mechanism ensures noise suppression when needed while avoiding unnecessary switching loss when the slew rate is already within acceptable ranges.
Solution Approach 2:
The system transitions from a static gate resistance design to a dynamic one where the gate resistance changes based on real-time operating conditions. This dynamic adjustment allows the system to maintain noise suppression guarantees while optimizing switching efficiency, as the gate resistance is only increased when the detected slew rate exceeds the target value.
3Object-generated harmful factors
If the slew rate of the drain voltage is reduced to suppress noise, then noise generation is decreased, but switching loss increases due to prolonged transition time
Solution Approach 1:
The patent changes the gate resistance parameter dynamically to control the slew rate. By adjusting the gate resistance value based on the detected actual slew rate and target slew rate comparison, the system can reduce noise generation when the slew rate is too high, while avoiding unnecessary energy loss when the slew rate is already appropriate. This parameter adjustment resolves the contradiction between noise suppression and switching loss.
Data Source
AI summary
A gate control circuit includes: a transition time detection circuit configured to detect a transition time of a drain voltage of a switching transistor that is turned ON or OFF by a gate voltage corresponding to a first pulse signal and a second pulse signal; an error detection circuit configured to output an error voltage representing a difference between the transition time and a target transition time being predetermined; and a transition time control circuit configured to generate the second pulse signal on the basis of the error voltage and the first pulse signal corresponding to an input signal that instructs ON or OFF of the switching transistor.