Gate Electrode Corner Rounding for Strain-Inducing Alloy Integration
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Solution Overview
Problem
The challenge in fabricating advanced integrated circuits is the increased leakage current and dependence on channel length due to short channel behavior in transistors with ultra-thin silicon dioxide gate insulation layers, which limits the scalability and performance of transistors, especially when using strain-inducing silicon/germanium alloys, where achieving high germanium concentration and lattice mismatch is difficult, leading to yield losses and irregularities.
Innovation Solution
The solution involves reducing the lateral offset of the strain-inducing semiconductor alloy from the channel region by using a reduced spacer width and modifying the etch and oxidation behavior to achieve corner rounding of the gate electrode material, thereby increasing the strain-inducing effect without compromising the integrity of the electrode material and reducing the probability of material residues during selective epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is scaled down to improve switching speed and drive current capability, then transistor performance increases, but leakage current increases exponentially due to direct tunneling through the ultra-thin gate oxide
Solution Approach 1:
The patent changes the material parameter of the gate insulation layer from conventional silicon dioxide to high-k dielectric materials (such as hafnium oxide, tantalum oxide). This material substitution allows the gate dielectric to maintain adequate capacitance for fast switching while providing physically greater thickness that blocks direct tunneling, thereby reducing leakage current. The high-k material's superior dielectric constant compensates for the increased thickness, preserving capacitive coupling between gate and channel.
Solution Approach 2:
The patent employs composite gate dielectric structures combining high-k dielectric materials with other materials (such as silicon nitride, silicon oxide) in multi-layer configurations. This composite approach optimizes both the capacitive coupling for speed and the tunneling barrier for leakage reduction, achieving a balance between switching performance and leakage control that neither material could provide alone.
2Power
If the thickness of the silicon dioxide gate insulation layer is decreased to provide required capacitance for short channel transistors, then capacitive coupling increases, but leakage current increases due to direct tunneling
Solution Approach 1:
The patent fundamentally changes the dielectric constant parameter by substituting silicon dioxide with high-k dielectric materials. This allows the gate dielectric to achieve the necessary capacitance (C = kε₀A/d) through material property (high k value) rather than by reducing thickness, thereby maintaining capacitive coupling while increasing physical thickness to block tunneling.
3Manufacturing precision
If the spacer width is reduced to decrease the lateral offset of the strain-inducing alloy from the channel region, then strain-inducing effect increases, but the integrity of the gate electrode material at the top corner is compromised
Solution Approach 1:
The patent applies preliminary corner rounding treatment to the gate electrode structure before forming the spacer layer. This pre-shaping action creates a rounded corner geometry that prevents the spacer from completely bridging the gap at the top corner, thereby maintaining gate electrode integrity even with reduced spacer width. The preliminary geometric modification enables subsequent process steps to proceed without compromising structural reliability.
Solution Approach 2:
The patent applies different geometric qualities to different parts of the gate electrode: the main body maintains sharp edges for proper alignment, while the top corners are rounded locally. This local quality differentiation allows the spacer to be sufficiently narrow for high precision lateral offset control in the channel region while preventing complete bridging at the vulnerable corner areas, thus preserving gate integrity.
4Manufacturing precision
If the germanium concentration in the silicon/germanium alloy is increased to achieve higher lattice mismatch and strain-inducing effect, then transistor performance improves, but manufacturing difficulty increases and yield losses occur
Solution Approach 1:
The patent optimizes the germanium concentration parameter to achieve an optimal balance point. Rather than maximizing germanium content for highest strain effect, the patent selects a moderate concentration (e.g., 5-20 atomic percent) that provides sufficient lattice mismatch and strain-inducing effect while remaining within the manufacturable range for selective epitaxial growth, avoiding aggregation and yield losses associated with higher concentrations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the strain-inducing effect in transistors, improving conductivity and reducing yield losses, while maintaining the integrity of the gate electrode structure, thus achieving superior transistor performance without increasing leakage currents.
Implementation Method 1
performing an oxidation process to form an oxide liner on sidewalls of the silicon-based gate electrode material
Implementation Method 2
forming a strain-inducing silicon/germanium alloy in the semiconductor region by using the dielectric cap layer and the spacer as a growth mask
Data Source
AI summary
In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.