Gate-Coupled Polar Capacitor Stack for Dense Logic Routing
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Solution Overview
Problem
Integrating capacitors, including ferroelectric or paraelectric materials, on the same plane as interconnects of logic devices is challenging due to spacing issues, making it difficult to connect transistors and route interconnects effectively.
Innovation Solution
A shared plate electrode structure is used to couple multiple capacitors to a single transistor, allowing for flexible arrangement and connection without intersecting with neighboring metal lines, and a dual hydrogen barrier is implemented to protect the capacitors from hydrogen diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are integrated on the same plane as interconnects of logic devices, then charge storage capability is improved, but spacing between capacitors becomes constrained and routing interconnects becomes difficult
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional vertical stacking. Capacitors are formed in multiple tiers above the substrate, with upper capacitors positioned at different heights than lower capacitors. This vertical arrangement eliminates the need for complex lateral routing between capacitors, as they can be connected through vertical vias and shared plate electrodes, thereby resolving the routing complexity issue while maintaining high charge storage capability.
2Area of moving object
If spacing between capacitors is scaled to increase density, then device density is improved, but integration of connections between transistors and capacitors becomes challenging
Solution Approach 1:
The patent implements shared plate electrodes that are commonly shared between multiple capacitors. A single plate electrode can serve as the common electrode for multiple capacitor structures stacked vertically or arranged in close proximity. This merging approach reduces the total number of separate interconnect structures needed, simplifies the connection integration process, and enables tighter capacitor spacing while maintaining manufacturability.
3Reliability
If multiple capacitors are coupled to a single transistor, then capacitance shielding and resistance are improved, but the structure becomes more complex
Solution Approach 1:
The patent divides the capacitor array into multiple tiers or levels, with each tier containing one or more capacitors that can be independently connected to transistors. This segmentation allows for systematic organization of the capacitor-transistor connections, making the overall structure more manageable despite the high number of capacitors. The segmented approach also facilitates progressive capacitance shielding as each tier contributes to the overall shielding effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density memory devices with improved capacitance shielding and reduced resistance, while protecting the capacitors from hydrogen damage, thereby enhancing device performance and reliability.
Implementation Method 1
Gate coupled non-linear polar material based capacitors for memory and logic
Implementation Method 2
a dual hydrogen barrier is implemented to protect the capacitors from hydrogen diffusion
Data Source
AI summary
A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.