Gate-Coupled EPROM Cell for Printhead Identification
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Solution Overview
Problem
Inkjet printhead circuits face challenges with existing identification methods, such as fuses being unreliable and prone to damage, and EPROM chips requiring additional layers and increased complexity, which complicates the provision of identification information necessary for proper printer operation without increasing interconnections or die size.
Innovation Solution
A gate-coupled EPROM structure is integrated into the printhead circuitry, utilizing existing layers to provide EPROM functionality without adding process steps or cost, allowing for efficient storage and retrieval of identification information using a compact layout that replaces fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuses are used for identification bits, then the circuit can be programmed, but the fuses are unreliable and can damage the inkjet orifice layer
Solution Approach 1:
The patent extracts the problematic fuse element from the circuit and replaces it with an EPROM-based identification bit that achieves the same programming function without the reliability issues of fuses. The EPROM cell structure eliminates the need for physical fuse burning while maintaining programmability.
Solution Approach 2:
The patent changes the programming mechanism from physical destruction (fuse burning) to electrical parameter modification (threshold voltage change in EPROM). By using voltage thresholds to represent binary states, the system achieves programmability without the harmful effects of fuse burning.
2Reliability
If EPROM chips are used for identification, then reliability improves compared to fuses, but additional layers and complexity are required
Solution Approach 1:
The patent merges the EPROM identification cell with the existing printhead circuit layers, integrating the floating gate and control gate structures into the same die without requiring separate EPROM chips or additional process layers. This combining approach maintains reliability while reducing complexity.
Solution Approach 2:
The patent makes the printhead die structure multi-functional by enabling it to serve both as the inkjet firing circuit and as an EPROM storage device. The same physical layers are used for both identification storage and circuit operation, eliminating the need for separate dedicated EPROM layers.
3Loss of information
If more identification information is provided, then printer operation can be optimized, but the die size or interconnections must increase
Solution Approach 1:
The patent utilizes the vertical dimension by implementing multiple identification bits stacked in different layers of the die structure. Rather than expanding horizontally, the system stores multiple bits of identification information by using the third dimension (depth/layers) of the semiconductor structure.
Solution Approach 2:
The patent segments the identification information into multiple individual bits, each stored in a separate EPROM cell structure. This segmentation allows for scalable information storage where additional identification data can be added by incorporating more bits without requiring a proportional increase in overall die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and efficiency of identification information storage in inkjet printheads, reducing the risk of damage and complexity, while maintaining a compact design that supports accurate printer operation and optimization.
Implementation Method 1
a floating gate and a control gate. The floating gate is separated from the control gate by a thin oxide layer that acts as a dielectric. A blank EPROM has all of the gates fully open, giving each cell a value of 1. That is, the floating gate initially has no charge, which causes the threshold voltage to be low.
Implementation Method 2
To change the value of the bit to 0, a programming voltage (e.g. 10 to 16 volts) is applied to the control gate and drain. This programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage. The excited electrons are pushed through and trapped on the other side of the thin oxide layer, giving it a negative charge.
Implementation Method 3
The floating gate is separated from the control gate by a thin oxide layer that acts as a dielectric.
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
An EPROM cell (270) in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer (256) and a conductive layer (260) disposed above the polysilicon layer, includes a control transistor (272) and an EPROM transistor (274). The control and EPROM transistors each have floating gates (280, 282) comprising a portion of the polysilicon layer (256), and an electrical interconnection, comprising a portion of the conductive layer (260), interconnects the floating gate (280) of the control transistor (272) and the floating gate (282) of the EPROM transistor (274).