Gate-Coupled ESD Protection Circuit With Buried-Layer Capacitor
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits in integrated circuits often occupy significant area and footprint, which can hinder their effectiveness and integration in electronic devices, as they fail to efficiently manage sudden and large current flows from ESD events without compromising the integrity of electrical components.
Innovation Solution
The integration of a gate-coupled transistor cell within the ESD protection circuit, featuring a transistor, effective capacitance, and resistance, where the effective capacitance is electrically coupled between the drain and gate of the transistor, and the effective resistance is coupled between the source and gate, utilizing a doped buried layer and capacitors in the semiconductor substrate to reduce the circuit's footprint and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ESD protection circuits are used, then charge dissipation function is provided, but footprint and area are large
Solution Approach 1:
The capacitor structure extends vertically through multiple semiconductor layers from the surface to the doped buried layer, utilizing the vertical dimension to achieve compact footprint while maintaining effective capacitance for ESD protection
Solution Approach 2:
The capacitor electrodes are embedded within the semiconductor substrate structure, with the first capacitor electrode extending from the surface through multiple layers to contact the doped buried layer, nesting the capacitance function within the existing device architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively dissipates ESD-induced current flows while maintaining a reduced footprint, enhancing the protection of electrical components by allowing charge dissipation through the transistor's conducting state and utilizing the capacitance to manage voltage spikes, thereby minimizing damage from ESD events.
Implementation Method 1
The capacitor includes a first capacitor electrode and a second capacitor electrode. The first and second capacitor electrodes extend from a top surface of the semiconductor layer to the doped buried layer. The capacitor further includes a capacitor dielectric layer disposed between the first capacitor electrode and the second capacitor electrode.
Implementation Method 2
The doped buried layer has the first conductivity type disposed in the semiconductor layer below the source region and the drain region. The doped buried layer is electrically coupled to the source region and the gate structure.
Implementation Method 3
The transistor includes a source region, a drain region, and a gate structure. The source region and the drain region have a first conductivity type and are disposed in a semiconductor layer.
Data Source
AI summary
The present disclosure generally relates to an electrostatic discharge (ESD) protection circuit in an integrated circuit and methods of forming such. In an example, an integrated circuit includes a transistor, a doped buried layer, and a capacitor. The transistor includes source and drain regions and a gate structure. The source and drain regions have a first conductivity type and are disposed in a semiconductor layer. The semiconductor layer has an opposite second conductivity type. The doped buried layer has the first conductivity type disposed in the semiconductor layer below the source and drain regions. The capacitor is disposed in the semiconductor layer and includes first and second capacitor electrodes extending to the doped buried layer. The first capacitor electrode electrically couples the drain region. The second capacitor electrode electrically couples the gate structure and conductively contacts the doped buried layer. The doped buried layer electrically couples the source region.